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EP20K100E Datasheet(PDF) 11 Page - Altera Corporation |
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EP20K100E Datasheet(HTML) 11 Page - Altera Corporation |
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11 / 117 page  Altera Corporation 11 APEX 20K Programmable Logic Device Family Data Sheet Logic Array Block Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains, LAB control signals, and the local interconnect. The local interconnect transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs. The Quartus II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of a fast local interconnect for high performance. Figure 3 shows the APEX 20K LAB. APEX 20K devices use an interleaved LAB structure. This structure allows each LE to drive two local interconnect areas. This feature minimizes use of the MegaLAB and FastTrack interconnect, providing higher performance and flexibility. Each LE can drive 29 other LEs through the fast local interconnect. Figure 3. LAB Structure To/From Adjacent LAB, ESB, or IOEs To/From Adjacent LAB, ESB, or IOEs The 10 LEs in the LAB are driven by two local interconnect areas. These LEs can drive two local interconnect areas. Local Interconnect LEs drive local MegaLAB, row, and column interconnects. Column Interconnect Row Interconnect MegaLAB Interconnect |
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