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EP2SGX130G Datasheet(PDF) 11 Page - Altera Corporation |
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EP2SGX130G Datasheet(HTML) 11 Page - Altera Corporation |
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11 / 36 page  Functional Description Page 11 Enhanced Configuration (EPC) Devices Datasheet January 2012 Altera Corporation Multiple FPGAs can be configured using a single EPC device in FPP mode. In this mode, multiple Stratix series FPGAs, APEX II FPGAs, or both, are cascaded together in a daisy chain. After the first FPGA completes configuration, its nCEO pin asserts to activate the nCE pin for the second FPGA, which prompts the second device to start capturing configuration data. In this setup, the FPGAs CONF_DONE pins are tied together, and hence all devices initialize and enter user mode simultaneously. If the EPC device or one of the FPGAs detects an error, configuration stops (and simultaneously restarts) for the whole chain because the nSTATUS pins are tied together. 1 While Altera FPGAs can be cascaded in a configuration chain, the EPC devices cannot be cascaded to configure larger devices or chains. f For more information about configuration schematics and multi-device FPP configuration, refer to the configuration chapter in the appropriate device handbook. Passive Serial Configuration APEX 20KC, APEX 20KE, APEX 20K, APEX II, Cyclone series, FLEX 10K, and Stratix series devices can be configured using EPC devices in the PS mode. This mode is similar to the FPP mode, with the exception that only one bit of data (DATA[0]) is transmitted to the FPGA per DCLK cycle. The remaining DATA[7..1] output pins are unused in this mode and driven low. The configuration schematic for PS configuration of a single FPGA or single-serial chain is identical to the FPP schematic, with the exception that only DATA[0] output from the EPC device connects to the FPGA DATA0 input pin and the remaining DATA[7..1] pins are left floating. f For more information about configuration schematics and multi-device PS configuration, refer to the configuration chapter in the appropriate device handbook. Concurrent Configuration EPC devices support concurrent configuration of multiple FPGAs (or FPGA chains) in PS mode. Concurrent configuration is when the EPC device simultaneously outputs n bits of configuration data on the DATA[n-1..0] pins (n = 1, 2, 4, or 8), and each DATA[] line serially configures a different FPGA chain. The number of concurrent serial chains is user-defined using the Quartus II software and can be any number from 1 to 8. For example, for three concurrent chains, you can select the 4-bit PS mode and connect the least significant DATA bits to the FPGAs or FPGA chains. Leave the most significant DATA bit (DATA[3]) unconnected. Similarly, for 5-, 6-, or 7-bit concurrent chains you can select the 8-bit PS mode. f For more information about configuration interface connections including pull-up resistor values, supply voltages, and MSEL pin settings, refer to the configuration chapter in the appropriate device handbook. |
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