AS2524BF datasheet(11/20 Pages) AMSCO

Part #	AS2524BF

Description	Telephone Line Interface and Speakerphone Circuit

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Manufacturer	AMSCO [ams AG]

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Data Sheet AS2523, AS2524, AS2524B

austriamicrosystems

Revision 1.13

Page 10 of 19

Programming Guidelines for the AS2523

The AS2523 is programmed by means of a serial 8-bit shift

register. MSB is clocked in first, LSB last.

The first four bits (7,6,5,4) are the addresses of the

registers, the last four bits (3,2,1,0) are the data bits.

Each register has a default setting (see data sheet), which

is set after power-up of the chip.

The internal registers are RAM-cells. When the AS2523

loses VDD (as in on-hook state) it also loses the register

contents.

It is therefore necessary to re-write the affected registers

after each hook event. The register contents cannot be

read, they can only be written.

Registers need to be re-written after each power-up and

after each hook event (handset / handsfree / on-hook).

It is recommended to always initialize the chip with a “reset

to defaults command” (Fx) first and then write the

appropriate registers that need to be changed from the

default setting.

Alternatively, all registers (4 to 16) may be re-written in a

bulk at each power-up and hook event (handset /

handsfree / on-hook).

This guarantees safe operation in case of unexpected loss

of power during normal operation. Re-writing all registers

also eases later software updates, as only register

contents need to be changed, but no additional command

lines need to be inserted.

Example of a typical power-up sequence

A typical power-up sequence will require the following

programming.

a) determine the cause of power-up (handset / handsfree

mode) and set register D accordingly.

Default = handset mode

b) Set the LI voltage to 3.5V or 4.5V (default = 4.5V) and

Line Loss Compensation (default = off) in register 4

c) Set the Confidence Tone level (e.g. the DTMF level

which is audible in the handset) and path in register 5

Default = off

d) Set the required Tx and Rx gains in Registers A and B

Default = 37dB Tx gain, 1dB Rx gain

Additional settings in Handsfree mode

Note: change the default settings only if necessary:

a) A click-free startup can be achieved by starting up in

handset mode (=default) and then switching to

handsfree, once the chip has stabilized.

b) Change the Tx comparator preamplifier gain in register 6

Default = 14dB

c) Change the Receive DC offset and Background noise

monitoring in Register 7

default = 0mV offset (higher val. puts more weight on Rx)

switching delay default = on

Background Noise Monitoring = on

d) Set the speaker amplifier volume in register 8

Default = 0B

e) Set the handsfree voice switching speed and

Background Noise monitoring offset in register 9:

default voice switching speed = 1ms/6dB (fastest)

default BGN monitoring offset = 240mV (determines the

Tx level required to switch from idle to Transmit)

Additional settings during Flash

During a Flash, the AS2523 should be powered down to

avoid discharge of VDD:

Set the MASK bit (bit3 in register D) to 1

After the line current is restored, the MASK bit must be

cleared again. Other settings do not need to be re-written,

as VDD has not discharged. As a safety margin however, it

is recommended to re-write all registers after a flash

Additional settings during line breaks

If a line-break-detection (brief interruption of the line while

in off-hook state) is implemented, the same rules apply as

for a Flash: set the MASK bit to 1 to avoid discharge of

VDD. It is recommended to re-write all registers after a

line-break, as a line break may take long enough to

discharge VDD, even when the MASK bit was set.

General Rules

The serial interface may be programmed at any time, it

does not affect the speech quality, e.g. if a register is

overwritten with the same value.

It is also possible to re-write all registers periodically. The

register is static, therefore it can be clocked at any speed

up to 5MHz.

However, electromagnetic pulses on the clock and data

lines may cause unwanted programming of the chip. It is

therefore recommended to keep these lines short, filter

them by a discrete lowpass filter and reduce the clock

speed accordingly.

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