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MAX1270BCNG Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX1270BCNG Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 20 page Multirange, +5V, 8-Channel, Serial 12-Bit ADCs 6 _______________________________________________________________________________________ Note 1: Accuracy specifications tested at VDD = +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply rejection test. Note 2: External reference: VREF = 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB. Note 3: Ground “on” channel; sine wave applied to all “off” channels. VIN = ±5V (MAX1270), VIN = ±4V (MAX1271). Note 4: Guaranteed by design, not production tested. Note 5: Use static external loads during conversion for specified accuracy. Note 6: Tested using internal reference. Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges. Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6). Note 9: Not production tested. Provided for design guidance only. TIMING CHARACTERISTICS (VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = +4.096V; 4.7µF at REF; external clock; fCLK = 2.0MHz (MAX127_B); fCLK = 1.8MHz (MAX127_A); TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) (Figures 2, 5, 7, 10) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIN to SCLK Setup tDS 100 ns DIN to SCLK Hold tDH 0ns SCLK Fall to Output Data Valid tDO 20 170 ns CS Fall to Output Enable tDV CLOAD = 100pF 120 ns CS Rise to Output Disable tTR CLOAD = 100pF 100 ns CS to SCLK Rise Setup tCSS 100 ns CS to SCLK Rise Hold tCSH 0ns SCLK Pulse-Width High tCH 200 ns SCLK Pulse-Width Low tCL 200 ns SCLK Fall to SSTRB tSSTRB CLOAD = 100pF 200 ns CS to SSTRB Output Enable tSDV CLOAD = 100pF, external clock mode only 200 ns CS to SSTRB Output Disable tSTR CLOAD = 100pF, external clock mode only 200 ns SSTRB Rise to SCLK Rise tSCK Internal clock mode only (Note 4) 0 ns |
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