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AS3931 Datasheet(PDF) 9 Page - ams AG |
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AS3931 Datasheet(HTML) 9 Page - ams AG |
9 / 31 page www.austriamicrosystems.com Revision 6.2 8 - 30 AS3931 Datasheet - Electrical Character i s t ics TDVCH Data valid to pos. Clock edge VREG = 2.4 V to 3.5 V 11 100 ns TCHDI pos. Clock edge to Data invalid VREG = 2.4 V to 3.5 V 11 100 ns TSHCH Select active to pos. Clock edge VREG = 2.4 V to 3.5 V 11 100 ns TCHSL pos. Clock to Select inactive VREG = 2.4 V to 3.5 V 11 100 ns TSL Select low time VREG = 2.4 V to 3.5 V 11 500 ns 1. The half-bit rate correlates with the crystal oscillator clock frequency fclk as follows: BR = fCLK/12 2. The Manchester bit rate correlates with the Half-Bit Rate as follows: BM = BR/2 3. Code word can be changed by metal option 4. 8 preamble half-bits are equivalent to 4 manchester bits 5. VREG output may not be used as a supply for other circuits 6. This is the internal Power on Reset time generated by the chip. To ensure proper start-up conditions, the supply voltage VCC must be ramped up to its final value during TPOR 7. This is the additional operating current when the RSSI buffer is activated without load 8. ΔVCC means a hard step of the supply voltage down to a lower value by an amount of ΔVCC; after such a step, the analog circuits in the chip take some time to recover for working properly again. The maximum step value is listed. 9. Crystal tolerance: 100ppm 10.Values refer to production test 11.If regulator is on, then VREG = 2.4 V; If regulator is off, then VREG = VCC, where VCC = 2.4 V to 3.5 V 12.The RSSI step is the change of the RSSI output voltage when the input signal amplitude changes from 0 to specified value 13.Time to step from initial RSSI value to 95% of the final value 14.ChA may be any channel 1 – 3, whereas ChB may be any other remaining channel. Table 3. Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units |
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