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PCM1727E2K Datasheet(PDF) 8 Page - Texas Instruments |
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PCM1727E2K Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 19 page  PCM1727 8 SBAS077A www.ti.com 1 2 3 14 15 1/f S L_ch R_ch MSB LSB 16 LRCIN (pin 19) BCKIN (pin 17) AUDIO DATA WORD = 16-BIT DIN (pin 18) 1 2 3 14 15 MSB LSB 16 1 2 3 18 19 MSB LSB 20 AUDIO DATA WORD = 20-BIT DIN (pin 18) 1 2 3 18 19 MSB LSB 20 2 1 2 1 2 1 1 2 3 22 23 MSB LSB 24 AUDIO DATA WORD = 24-BIT DIN (pin 18) 1 2 3 22 23 MSB LSB 24 system clock is specified at 150ps typical. Figure 3 illus- trates the timing requirements for the 27MHz master clock. Figure 4 illustrates the system clock connections for an external clock or crystal oscillator. The PCM1727 internal PLL can be programmed for three different sampling frequencies (LRCIN), as shown in Table I. The internal sampling clocks generated by the various programmed frequencies are shown in Table II. The system clock output frequency for PCM1727 is 100% accurate. To provide MCKO clock and SCKO1, SCKO2, SCKO3 clocks for external circuits, an external buffer may be used to avoid degrading audio performance (as shown in the connection diagram, in Figure 1). Sampling Frequencies-LRCIN (kHz) Standard Sampling Freq 44.1 48 Double of Standard Sampling Freq 96 TABLE I. Sampling Frequencies. Sampling Frequency SCKO2 SCKO3 (LRCIN) System Clock System Clock 44.1kHz Standard 16.9344MHz 33.8688MHz 48kHz Standard 18.4320MHz 36.8640MHz 96kHz Double 36.8640MHz 36.8640MHz TABLE II. Sampling Frequencies vs Internal System Clock (= Output Frequencies of Dual PLL). FIGURE 7. Audio Data Input Timing. LRCKIN BCKIN DIN 1.4V 1.4V 1.4V t BCH t BCL t LB t BL t DS BCKIN Pulse Cycle Time BCKIN Pulse Width High BCKIN Pulse Width Low BCKIN Rising Edge to LRCIN Edge LRCIN Edge to BCKIN Rising Edge DIN Set-up Time DIN Hold Time : t BCY : t BCH : t BCL : t BL : t LB : t DS : t DH : 100ns (min) : 50ns (min) : 50ns (min) : 30ns (min) : 30ns (min) : 30ns (min) : 30ns (min) t DH t BCY FIGURE 6. I2S Data Input Timing. |
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