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AT17C010A-10JI Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT17C010A-10JI Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 11 page AT17C/LV/512A/010A 2 Block Diagram Device Configuration The control signals for configuration EEPROMs–nCS, OE, and DCLK–interface directly with the FPGA device control signals. All FPGA devices can control the entire configura- tion process and retrieve data from the configuration EEPROM without requiring an external intelligent control- ler. The configuration EEPROM device’s OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter and the oscillator. When OE is driven low, the configuration EEPROM device resets the address counter and tri-states its DATA pin. The nCS pin controls the output of the AT17A Series. If nCS is held high after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven low, the counter and the DATA output pin are enabled. When OE is driven low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS. When the configurator has driven out all of its data and nCASC is driven low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. FPGA Device Configuration FPGA devices can be configured with an AT17A Series EEPROM. The AT17A Series device stores configuration data in its EEPROM array and clocks the data out serially with its internal oscillator. The OE, nCS, and DCLK pins supply the control signals for the address counter and the output tri-state buffer. The AT17A Series device sends a serial bitstream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the FPGA device. When configuration data for a FPGA device exceeds the capacity of a single AT17A Series device, multiple AT17A Series devices can be serially linked together. When multi- ple AT17A Series devices are required, the nCASC and nCS pins provide handshaking between the AT17A Series devices. The position of an AT17A Series device in a chain deter- mines its operation. The first AT17A Series device in a Configurator chain is powered up or reset with nCS low and is configured for FPGA devices protocol. This AT17A Series device supplies all clock pulses to one or more FPGA devices and to any downstream AT17A Series dur- ing configuration. The first AT17A Series device also pro- vides the first stream of data to the FPGA devices during EEPROM CELL MATRIX ROW DECODER COLUMN DECODER TC 5 11 24/32 24/32 nCS DCLK OE nCASC DATA BIT COUNTER OSC OSC CONTROL PROGRAMMING DATA SHIFT REGISTER PROGRAMMING MODE LOGIC ROW ADDRESS COUNTER SER_EN |
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