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P3PS850BH Datasheet(PDF) 2 Page - ON Semiconductor |
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P3PS850BH Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 12 page P3PS850BH http://onsemi.com 2 VDD GND SSEXTR CLKIN ModOUT (Timing−Safe) PLL FS PD#/OE MR Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin# Pin Name Type Description 1 CLKIN I External reference Clock input. 2 PD# / OE I Power Down. Pull LOW to enable Power Down. Outputs will be tri−stated when power down is en- abled. Pull HIGH to disable power down and enable output. NO default state. 3 FS I Frequency Select .NO default state. Refer to the Frequency Selection table 4 GND P Ground 5 ModOUT O Buffered modulated Timing−Safe clock output 6 MR I Modulation Rate Select. When LOW, selects Low Modulation Rate. Selects High Modulation Rate when pulled HIGH. Has an internal pull−up resistor. 7 SSEXTR I Analog Deviation Selection through external resistor to GND. 8 VDD P Supply Voltage Table 2. FREQUENCY SELECTION TABLE FS Frequency (MHz) 0 18−36 1 36−72 Table 3. OPERATING CONDITIONS Symbol Parameter Min Max Unit VDD Supply Voltage 2.3 3.6 V TA Operating Temperature −20 +85 °C CL Load Capacitance 15 pF CIN Input Capacitance 7 pF |
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