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DP83620SQE Datasheet(PDF) 9 Page - Texas Instruments |
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DP83620SQE Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 105 page  DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 Signal Name Pin Name Type Pin # Description CRS/CRS_DV CRS/CRS_DV S, O, PU 40 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification. This pin provides an integrated 50 ohm signal termination, making external termination resistors unnecessary. COL COL S, O, PU 42 MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test). In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10 Mb/s full duplex operation. RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. This pin provides an integrated 50 ohm signal termination, making external termination resistors unnecessary. 3.5 CLOCK INTERFACE Signal Name Pin Name Type Pin # Description X1 X1 I 34 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83620 and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83620 supports either an external crystal resonator connected across pins X1 and X2 or an external CMOS-level oscillator source connected to pin X1 only. RMII REFERENCE CLOCK: For RMII Slave Mode, this pin must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source. In RMII Master Mode, a 25 MHz reference is required, either from an external crystal resonator connected across pins X1 and X2 or from an external CMOS-level oscillator source connected to pin X1 only. X2 X2 O 33 CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS oscillator clock source is used. CLK_OUT CLK_OUT O 24 CLOCK OUTPUT: This pin provides a highly configurable system clock, which may have one of three sources: 1. 50 MHz RMII reference clock in RMII Master Mode 2. 25 MHz Receive Clock (same as RX_CLK) in 100 Mb mode 3. 25 MHz or 50 MHz pass-through of X1 reference clock 3.6 LED INTERFACE The DP83620 supports three configurable LED pins. The LEDs support two operational modes which are selected by the LED mode strap and a third operational mode which is register configurable. The definitions for the LEDs for each mode are detailed below. Signal Name Pin Name Type Pin # Description LED_LINK LED_LINK S, O, PU 28 LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good. LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active. LED_SPEED LED_SPEED/FX_S S, O, PU 27 SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in D 10 Mb/s. Functionality of this LED is independent of mode selected. LED_ACT LED_ACT S, O, PU 26 ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity is present on either Transmit or Receive. COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. In Mode 3, this LED output indicates Full-Duplex status. Copyright © 2011–2013, Texas Instruments Incorporated Pin Descriptions 9 Submit Documentation Feedback Product Folder Links: DP83620 |
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