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DRV103U2K5 Datasheet(PDF) 9 Page - Texas Instruments |
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DRV103U2K5 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 24 page  DRV103 9 SBVS029A A 100pF capacitor in parallel with RPWM is recommended when switching a high load current to maintain a clean output switching waveform, as shown in Figure 6. The DRV103’s adjustable PWM output frequency allows it to be optimized for driving virtually any type of load. ADJUSTABLE DUTY CYCLE (PWM Mode) The DRV103’s externally adjustable duty cycle provides an accurate means of controlling power delivered to a load. Duty cycle can be set over a range of at least 10% to 90% with an external resistor, analog voltage, or the voltage output of a D/A converter. A low duty cycle results in reduced power dissipation in the load. This keeps the DRV103 and the load cooler, resulting in increased reliability for both devices. Resistor Controlled Duty Cycle Duty cycle is easily programmed by connecting a resistor (RPWM) between the Duty Cycle Adjust pin (pin 1) and ground. High resistor values correspond to high duty cycles. Table III provides resistor values for typical duty cycles. Resistor values for additional duty cycles can be obtained from Figure 5. For reference purposes, the equation for calculating RPWM is included in Figure 5. DUTY CYCLE RPWM (Nearest 1% Values) (%) 5kHz 25kHz 100kHz 5 374k 75k 16.9k 10 402k 80.6k 19.1k 20 475k 95.3k 22.6k 30 549k 110k 26.1k 40 619k 124k 29.4k 50 681k 137k 33.2k 60 750k 150k 37.4k 70 825k 165k 40.2k 80 887k 182k 44.2k 90 953k 196k 47.5k 95 1M 200k 49.9k TABLE III. Duty Cycle Adjust Resistance. FIGURE 5. Using a Resistor to Program Duty Cycle. At 25kHz: RPWM (kΩ) = 67.46 + 1.41 • %DC. 1M 100k 10k 20 40 0 60 80 100 DUTY CYCLE vs R PWM Duty Cycle (%) 5kHz 25kHz 100kHz R PWM only on Pin 1 With 100pF in Parallel with R PWM Time (10 µs) FIGURE 6. Output Waveform at High Load Current. 100 90 80 70 60 50 40 30 20 10 0 2 1 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 34 DUTY CYCLE AND DUTY CYCLE ERROR vs VOLTAGE V PWM (V) FIGURE 7. Using a Voltage to Program Duty Cycle. At VS = 24V and F = 25kHz: VPWM = 1.25 + 0.026 • %DC. Voltage Controlled Duty Cycle Duty cycle can also be programmed by an analog voltage, VPWM. With VPWM ≈ 3.56V, duty cycle is about 90%. Decreasing this voltage results in decreased duty cycles. Table IV provides VPWM values for typical duty cycles. The “Duty Cycle vs Voltage” typical performance curve for additional duty cycles is shown in Figure 7. DUTY CYLE VPWM (%) (V) 5 1.344 10 1.518 20 1.763 40 2.283 60 2.788 80 3.311 90 3.561 95 3.705 TABLE IV. Duty Cycle Adjust Voltage. |
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