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DS90UB904Q Datasheet(PDF) 10 Page - Texas Instruments |
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DS90UB904Q Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 45 page  DS90UB903Q, DS90UB904Q SNLS332E – JUNE 2010 – REVISED APRIL 2013 www.ti.com Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tLHT CML Low-to-High Transition RL = 100Ω (Figure 6) 150 330 ps Time tHLT CML High-to-Low Transition RL = 100Ω (Figure 6) 150 330 ps Time tDIS Data Input Setup to PCLK 2.0 ns Serializer Data Inputs (Figure 12) tDIH Data Input Hold from PCLK 2.0 ns tPLD Serializer PLL Lock Time RL = 100Ω (1) (2) 1 2 ms tSD RT = 100Ω, PCLK = 10–43 MHz 6.386T 6.386T 6.386T Serializer Delay Register 0x03h b[0] (TRFB = 1) ns + 5 + 12 + 19.7 (Figure 14) tJIND Serializer output intrinsic deterministic Serializer Output jitter . Measured (cycle-cycle) with 0.13 UI Deterministic Jitter PRBS-7 test pattern PCLK = 43 MHz(3)(4) tJINR Serializer output intrinsic random jitter Serializer Output Random (cycle-cycle). Alternating-1,0 pattern. 0.04 UI Jitter PCLK = 43 MHz(3)(4) tJINT Serializer output peak-to-peak jitter includes deterministic jitter, random Peak-to-peak Serializer jitter, and jitter transfer from serializer 0.396 UI Output Jitter input. Measured (cycle-cycle) with PRBS-7 test pattern. PCLK = 43 MHz(3)(4) λSTXBW Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 1.90 MHz Function -3 dB Bandwidth (Figure 20)(3) δSTX Serializer Jitter Transfer PCLK = 43 MHz, Default Registers 0.944 dB Function (Peaking) (Figure 20)(3) δSTXf Serializer Jitter Transfer PCLK = 43 MHz, Default Registers Function (Peaking 500 kHz (Figure 20)(3) Frequency) (1) tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK (2) Specification is ensured by design. (3) Typical values represent most likely parametric norms at 1.8V or 3.3V, TA = +25°C, and at the Recommended Operation Conditions at the time of product characterization and are not ensured. (4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency. Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP Receiver Output Clock Period tRCP = tTCP PCLK 23.3 T 100 ns tPDC Default Registers PCLK Duty Cycle PCLK 45 50 55 % SSCG[3:0] = OFF LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or tCLH 1.3 2.0 2.8 Time 3.0 to 3.6V, CL = 8 pF (lumped load) PCLK ns tCHL LVCMOS High-to-Low Transition Default Registers 1.3 2.0 2.8 Time (Figure 16)(1) LVCMOS Low-to-High Transition VDDIO: 1.71V to 1.89V or tCLH 1.6 2.4 3.3 Time 3.0 to 3.6V, Deserializer ROUTn CL = 8 pF (lumped load) ns tCHL Data Outputs LVCMOS High-to-Low Transition Default Registers 1.6 2.4 3.3 Time (Figure 16)(1) tROS ROUT Setup Data to PCLK VDDIO: 1.71V to 1.89V or 0.38T 0.5T 3.0V to 3.6V, Deserializer ROUTn tROH ns CL = 8 pF (lumped load) Data Outputs ROUT Hold Data to PCLK 0.38T 0.5T Default Registers (1) Specification is ensured by characterization and is not tested in production. 10 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated Product Folder Links: DS90UB903Q DS90UB904Q |
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