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DS92LV3241TVS Datasheet(PDF) 11 Page - Texas Instruments |
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DS92LV3241TVS Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 31 page  DS92LV3241, DS92LV3242 www.ti.com SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tROCP Receiver Output Clock Period tROCP = tCIP (Dual Mode) 20 tROCP 50 Figure 11 ns tROCP = tCIP 11.76 tROCP 25 (Quad Mode) tRODC RxCLKOUT Duty Cycle 45 50 55 % tROTR LVCMOS Low-to-High Transition CL = 8pF (lumped load) 3.2 ns Time (Dual Mode) Figure 10 tROTF LVCMOS High-to-Low Transition 3.5 ns Time tROTR LVCMOS Low-to-High Transition CL = 8pF (lumped load) ns 2.4 Time (Quad Mode) tROTF LVCMOS High-to-Low Transition ns 1.9 Time tROSC RxOUT[31:0] Setup to RxCLKOUT f = 50 MHz 0.5 x 5.6 ns (Dual Mode) tROCP tROHC RxOUT[31:0] Hold to RxCLKOUT 0.5 x 7.4 ns tROCP tROSC RxOUT[31:0] Setup to RxCLKOUT f = 85 MHz 0.5 x 3.4 ns (Quad Mode) tROCP tROHC RxOUT[31:0] Hold to RxCLKOUT 0.5 x 3.4 ns tROCP tHZR Data Output High to TRI-STATE Figure 13 5 10 ns Delay tLZR Data Output Low to TRI-STATE 5 10 ns Delay tZHR Data Output TRI-STATE to High 5 10 ns Delay tZLR Data Output TRI-STATE to Low 5 10 ns Delay tRD Deserializer Propagation Delay – f = 20 MHz 5.5 x ns Latency (Dual Mode) tROCP + Figure 12 3.35 5.5 x ns f = 50 MHz tROCP + (Dual Mode) 6.00 12.0 x ns f = 40 MHz tROCP + (Quad Mode) 7.4 12.0 x ns f = 85 MHz tROCP + (Quad Mode) 5.7 tRPLLS (1) Deserializer PLL Lock Time 20 MHz – 50 MHz 128k x (Dual Mode) ns tROCP Figure 13 40 MHz – 85 MHz 256k x (Quad Mode) ns tROCP Figure 13 TOLJIT Deserializer Input Jitter Tolerance 0.25 UI tLVSKR LVDS Differential Input Skew 20 MHz – 85 MHz 0.4 x ns Tolerance Figure 17 tROCP (1) tRPLLS is the time required by the Deserializer to obtain lock when exiting power-down mode. Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DS92LV3241 DS92LV3242 |
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