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AT17LV65-10JI Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT17LV65-10JI Datasheet(HTML) 4 Page - ATMEL Corporation |
4 / 10 page AT17 Series 4 FPGA Master Serial Mode Summary The I/O and logic functions of the FPGA and their associ- ated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Mode, the FPGA auto- matically loads the configuration program from an external memory. The Serial Configuration EEPROM has been designed for compatibility with the Master Serial Mode. Cascading Serial Configuration EEPROMs (AT17C/LV128 and AT17C/LV256) For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cas- caded Configurators provide additional memory (17C/ LV128 and 17C/LV256 only). After the last bit from the first Configurator is read, the next clock signal to the Configurator asserts its CEO output Low and disables its DATA line. The second Configurator recog- nizes the Low level on its CE input and enables its DATA output. Figure 1. Condition 1 Connection After configuration is complete, the address counters of all cascaded Configurators are reset if the reset signal drives the RESET/OE on each Configurator Active. If the address counters are not to be reset upon comple- tion, then the RESET/OE inputs can be tied to ground. For more details, please reference the AT17C Series Program- ming Guide. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2- wire interface. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. See the Programming Specification for Atmel's Con- figuration Memories Application Note for further informa- tion. The AT17C Series parts are read/write at 5V nominal. The AT17LV parts are read/write at 3.0V nominal. AT17C/LVXXX Reset Polarity The AT17C/LVXXX lets the user choose the reset polarity as either RESET/OE or RESET/OE. Standby Mode The AT17C/LVXXX enters a low-power standby mode whenever CE is asserted High. In this mode, the Configura- tor consumes less than 1.0 mA of current. The output remains in a high impedance state regardless of the state of the OE input. Operating Conditions Symbol Description AT17CXXX AT17LVXXX Units Min/Max Min/Max VCC Commercial Supply voltage relative to GND -0 °C to +70°C 4.75/5.25 3.0/3.6 V Industrial Supply voltage relative to GND -40 °C to +85C° 4.5/5.5 3.0/3.6 V Military Supply voltage relative to GND -55 °C to +125C 4.5/5.5 3.0/3.6 V |
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