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020-2955-XX Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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020-2955-XX Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 8 page DDR Memory Bus Electrical Validation and Analysis Software Additional Capabilities using a Performance MSO (Mixed-Signal Oscilloscope) The MSO70000 Series Performance MSOs allow you to probe more signals on the DDR bus and to trigger on and view specific bus events. Up to 16 digital channels can be used to view logic states of command and address signals such as RAS, CAS, WE, CE, CS, etc. Signal integrity of these 16 inputs can be analyzed using the iCapture™ multiplexing feature, which allows any of the digital input signals to be internally routed to one of the scope’s four analog channels. Measurements involving command-bus cycle timing can also be analyzed using the bus-decode features of the MSO and DDRA software. Full Bus Analysis using Logic Analyzer and Oscilloscope When full protocol analysis or probing of the entire memory bus is required, a logic analyzer can provide this additional capability. The TLA7000 Series logic analyzers can also be linked with Tektronix oscilloscopes to provide an integrated test setup using tools such as iCapture mentioned above. This eliminates the need for double probing and allows full analog capture of any signals probed by the logic analyzer. In addition, the iView™ display interface allows transfer of the oscilloscope data to the logic analyzer display, so that data from both instruments are analyzed and time-aligned on one display screen. Characteristics Bandwidth Recommendations for Each DDR Standard DDR Type Maximum Data Rate (JEDEC) Clock Rate 5th Harmonic of Clock Max SE Slew Rate (JEDEC) Typical Signal Swing Oscilloscope Rise Time 10% - 90%*1 Recommended Oscilloscope BW*2 DDR 400 MT/s 200 MHz 1GHz 5V/ns 1.8 V 89 ps 4GHz DDR2 800 MT/s 400 MHz 2GHz 5V/ns 1.25 V 62 ps 6GHz DDR3 2133 MT/s 1066 MHz 5.3 GHz 5 V/ns 1.0 V 49 ps 8GHz GDDR5 5 GT/s 2.5 GHz 12.5 GHz N/A 0.8 V 18 ps 20 GHz*3 *1 For 3% maximum error on rise-time measurement. *2 For less stringent applications, a one-step reduction in scope bandwidth may be acceptable. *3 Basedon5GT/s system; lowerBWscope maysuffice for lower data rates. Ordering Information DDRA DDR Memory Bus Electrical Validation and Analysis Oscilloscope Software. To order on a new DPO5000, MSO5000, DPO7000, DPO70000, DSA70000*4, or MSO70000 Series: Order Description Opt. DDRA Preinstall on a new DPO5000*5, MSO5000*5, DPO7000*5, DPO70000*5, DSA70000, or MSO70000*5 Series oscilloscope DPOFL-DDRA DDR Memory Technology Analysis Package – Floating License *4 Note: Opt. DJA and ASM are standard on the DSA70000 Series oscilloscopes. *5 Note: Opt. ASM (Advanced Event Search and Mark) and Opt. DJA (DPOJET) are required. To upgrade an existing DPO5000, MSO5000, DPO7000, DPO70000, DSA70000, or MSO70000 Series: Order Description DPO-UP DDRA Upgrade to Option DDRA (requires Opt. ASM and DJA) DPO-UP DJAE Upgrade MSO/DPO5000 Series with DPOJET Jitter and Eye Diagram Analysis (Opt. DJA) DPO-UP DJAM Upgrade DPO7000 with DPOJET Jitter and Eye Diagram Analysis (Opt. DJA) DPO-UP DJAH Upgrade DPO70404 - DPO70804 or MSO70404 - MSO70804 with DPOJET Jitter and Eye Diagram Analysis (Opt. DJA) DPO-UP DJAU Upgrade DPO71254 - DPO73304 or MSO71254 - MSO72004 with DPOJET Jitter and Eye Diagram Analysis (Opt. DJA) DPO-UP DJUP DJA DPOJET software for scopes with both TDSJIT3 and TDSRTE licenses Note: Software is supplied on the internal hard drive of the DPO5000, MSO5000, DPO7000, DPO70000, DSA70000, and MSO70000 Series oscilloscopes. User documentation (online or user manual) is part of the oscilloscope documentation. To order a floating license for an existing DPO5000, MSO5000, DPO7000, DPO70000, DSA70000, or MSO70000 Series: Order Description DPOFL-DDRA DDR Memory Technology Analysis Package – Floating License DPOFL-DJA DPOJET Jitter and Eye Diagram Analysis – Floating License www.tektronix.com 3 |
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