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AT28BV16-25TC Datasheet(PDF) 3 Page - ATMEL Corporation |
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AT28BV16-25TC Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 8 page Device Operation READ: The AT28BV16 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in a high im- pedance state whenever CE or OE is high. This dual line control gives designers increased flexibility in preventing bus contention. BYTE WRITE: Writing data into the AT28BV16 is similar to writing into a Static RAM. A low pulse on the WE or CE input with OE high and CE or WE low (respectively) initi- ates a byte write. The address location is latched on the last falling edge of WE (or CE); the new data is latched on the first rising edge. Internally, the device performs a self- clear before write. Once a byte write has been started, it will automatically time itself to completion. Once a pro- gramming operation has been initiated and for the dura- tion of tWC, a read operation will effectively be a polling operation. DATA POLLING: The AT28BV16 provides DATA POLLING to signal the completion of a write cycle. During a write cycle, an attempted read of the data being written results in the complement of that data for I/O7 (the other outputs are indeterminate). When the write cycle is fin- ished, true data appears on all outputs. READY/BUSY (TSOP only): READY/BUSY is an open drain output; it is pulled low during the internal write cycle and released at the completion of the write cycle. WRITE PROTECTION: Inadvertent writes to the device are protected against in the following ways. (a) Vcc sense— if Vcc is below 2.0V (typical) the write function is inhibited. (b) Vcc power on delay— once Vcc has reached 2.0V the device will automatically time out 5 ms (typical) before allowing a byte write. (c) Write Inhibit— holding any one of OE low, CE high or WE high inhibits byte write cy- cles. DEVICE IDENTIFICATION: A n ex t r a 32- bytes of E2PROM memory are available to the user for device identification. By raising A9 to 12 ± 0.5V and using ad- dress locations 7E0H to 7FFH the additional bytes may be written to or read from in the same manner as the regular memory array. AT28BV16 2-121 |
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