AT27LV1026

2

This device is internally architected as two 32K x 16 mem-

ory banks, odd and even. To begin a non-linear access

NLA cycle, (which typically equals a minimum of two linear

access LA cycles), ALE is asserted high and CS is

asserted low. The two internal 15-bit counters store the

address for the odd and even banks and increment alter-

nately during each subsequent linear access LA cycle. The

LA cycle will be terminated when CS is asserted high put-

ting the device in standby mode, or another NLA cycle

starts. The LA cycle can be resumed when CS is asserted

low and ALE stays low. The AT27LV1026 will continuously

output data within each LA cycle which is determined by

the read RD signal. Continuous interleave read operation is

possible as there is no physical limit to the linear access LA

output. When the last address in the array is reached the

counters will wrap around to the first address location and

continue.

For a NLA cycle where A0 = 0 (ALE asserted high, CS

asserted low), both even and odd counters will be loaded

with new address (A1 - A15). Outputs (O0 - O15) from the

even bank will be valid in t

the following LA cycle while the even counter increments

by one to ready the data out for the next LA cycle. The out-

puts will have even or odd data alternating and the

counters increment for the consecutive LA cycles until CS

is asserted high putting the device in standby mode, or a

new NLA cycle begins.

For a NLA cycle where A0 = 1 (ALE asserted high, CS

asserted low), the odd counter will be loaded with the new

address (A1 - A15) while the even counter gets loaded with

the new address+1. Outputs (O0 - O15) from odd bank of

memory will be valid in t

data output from the even bank of memory will become

valid in t

counter increments by one to ready the data out for the

next LA cycle. The outputs will have data from the odd or

even memory bank alternately and the counters increment

for the following consecutive LA cycles until CS is asserted

high putting the device in standby mode, or a new NLA

cycle begins. When coming out of standby mode, the

device can either enter into a new NLA cycle or resume

where the previous LA operation left off and was termi-

nated by standby mode.

System Considerations

Switching under active conditions may produce transient

voltage excursions. Unless accommodated by the system

design, these transients may exceed data sheet limits,

resulting in device non-conformance. At a minimum, a 0.1

µF high frequency, low inherent inductance, ceramic

capacitor should be utilized for each device. This capacitor

should be connected between the V

nals of the device, as close to the device as possible. Addi-

tionally, to stabilize the supply voltage level on printed cir-

cuit boards with large EPROM arrays, a 4.7

µF bulk elec-

trolytic capacitor should be utilized, again connected

between the V

should be positioned as close as possible to the point

where the power supply is connected to the array.

Operating Table

If A0 = 0 at beginning of NLA cycle:

If A0 = 1 at beginning of NLA cycle:

and so on.

and so on.

Consecutive

Cycle

Counter

Outputs

Consecutive

Cycle

Counter

Outputs

Even

Odd

Even

Odd

NLA

Address

Address

from Even Bank

NLA

Address+1

Address

from Odd Bank

LA

+1

-

from Odd Bank

LA

-

+1

from Even Bank

LA

-

+1

from Even Bank

LA

+1

-

from Odd Bank

LA

+1

-

from Odd Bank

LA

-

+1

from Even Bank

LA

-

+1

from Even Bank

LA

+1

-

from Odd Bank

Standby

HiZ

Standby

HiZ

LA

+1

-

from Odd Band

LA

-

+1

from Even Bank

LA

-

+1

from Even Bank

LA

+1

-

from Odd Band