Device Operation

READ: The AT28HC256 is accessed like a Static RAM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state when either CE or OE is high. This dual-

line control gives designers flexibility in preventing bus

contention in their system.

BYTE WRITE: A low pulse on the WE or CE input with CE

or WE low (respectively) and OE high initiates a write cy-

cle. The address is latched on the falling edge of CE or

WE, whichever occurs last. The data is latched by the first

rising edge of CE or WE. Once a byte write has been

started it will automatically time itself to completion. Once

a programming operation has been initiated and for the

ing operation.

PAGE WRITE: The p a g e wr i t e oper ation of the

AT28HC256 allows 1 to 64-bytes of data to be written into

the device during a single internal programming period. A

page write operation is initiated in the same manner as a

byte write; the first byte written can then be followed by 1

to 63 additional bytes. Each successive byte must be writ-

ten within 150

limit is exceeded the AT28C256 will cease accepting data

and commence the internal programming operation. All

bytes during a page write operation must reside on the

same page as defined by the state of the A6 - A14 inputs.

That is, for each WE high to low transition during the page

write operation, A6 - A14 must be the same.

The A0 to A5 inputs are used to specify which bytes within

the page are to be written. The bytes may be loaded in any

order and may be altered within the same load period.

Only bytes which are specified for writing will be written;

unnecessary cycling of other bytes within the page does

not occur.

DATA POLLING: The AT28HC256 features DATA Polling

to indicate the end of a write cycle. During a byte or page

write cycle an attempted read of the last byte written will

result in the complement of the written data to be pre-

sented on I/O7. Once the write cycle has been completed,

true data is valid on all outputs, and the next write cycle

may begin. DATA Polling may begin at anytime during the

write cycle.

TOGGLE BIT: I n ad di ti on t o DATA P o ll in g th e

AT28HC256 provides another method for determining the

end of a write cycle. During the write operation, succes-

sive attempts to read data from the device will result in

I/O6 toggling between one and zero. Once the write has

completed, I/O6 will stop toggling and valid data will be

read. Testing the toggle bit may begin at any time during

the write cycle.

(continued)

DATA PROTECTION: If precautions are not taken, inad-

vertent writes to any 5-volt-only nonvolatile memory may

occur during transition of the host system power supply.

Atmel has incorporated both hardware and software fea-

tures that will protect the memory against inadvertent

writes.

HARDWARE PROTECTION: Hardware features protect

against inadvertent writes to the AT28HC256 in the follow-

out 5 ms typical) before allowing a write: (c) write inhibit -

holding any one of OE low, CE high or WE high inhibits

write cycles; (d) noise filter - pulses of less than 15 ns (typi-

cal) on the WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software controlled

data protection feature has been implemented on the

AT28HC256. When enabled, the software data protection

(SDP), will prevent inadvertent writes. The SDP feature

may be enabled or disabled by the user; the AT28HC256

is shipped from Atmel with SDP disabled.

SDP is enabled by the host system issuing a series of

three write commands; three specific bytes of data are

written to three specific addresses (refer to Software Data

Protection Algorithm). After writing the 3-byte command

tected against inadvertent write operations. It should be

noted, that once protected the host may still perform a

byte or page write to the AT28HC256. This is done by pre-

ceding the data to be written by the same 3-byte command

sequence.

Once set, SDP will remain active unless the disable com-

mand sequence is issued. Power transitions do not dis-

able SDP and SDP will protect the AT28HC256 during

power-up and power-down conditions. All command se-

quences must conform to the page write timing specifica-

tions. It should also be noted that the data in the enable

and disable command sequences is not written to the de-

vice and the memory addresses used in the sequence

may be written with data in either a byte or page write op-

eration.

After setting SDP, any attempt to write to the device with-

out the three byte command sequence will start the inter-

nal write timers. No data will be written to the device; how-

tively be polling operations.

AT28HC256

2-281