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AT45D041 Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT45D041 Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 16 page AT45D041 7 AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both wavforms show valid timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3. Waveform 1 – Inactive Clock Polarity Low CS SCK SI SO tCSS VALID IN tH tSU tWH tWL tCSH tCS tV HIGH IMPEDANCE VALID OUT tHO tDIS HIGH IMPEDANCE Waveform 2 – Inactive Clock Polarity High CS SCK SI SO tCSS VALID IN tH tSU tWL tWH tCSH tCS tV HIGH Z VALID OUT tHO tDIS HIGH IMPEDANCE Command Sequence for Read/Write Operations (Except Status Register Read) Notes: 1. “r” designates bits reserved for larger densities. 2. It is recommended that “r” be a logical “0” for densities of 4M bit or smaller. 3. For densities larger than 4M bit, the “r” bits become the most significant Page Address bit for the appropriate density. SI CMD 8 bits 8 bits 8 bits MSB Reserved for larger densities Page Address (PA10-PA0) Byte/Buffer Address (BA8-BA0/BFA8-BFA0) LSB r r r r X X X X X X X X X X X X X X X X X X X X |
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