AT45D041

4

Buffer to Main Memory Page Program with Built-In Erase.

A page of data is first transferred from the main memory to

buffer 1 or buffer 2, and then the same data (from buffer 1

or buffer 2) is programmed back into its original page of

main memory. An 8-bit opcode, 58H for buffer 1 or 59H for

buffer 2, is followed by the four reserved bits, 11 address

bits (PA10-PA0) that specify the page in main memory to

be rewritten, and nine additional don't care bits. When a

low to high transition occurs on the CS pin, the part will first

transfer data from the page in main memory to a buffer and

then program the data from the buffer back into same page

of main memory. The operation is internally self-timed and

should take place in a maximum time of t

time, the status register will indicate that the part is busy.

If the main memory is programmed or reprogrammed

sequentially page by page, then the programming algo-

rithm shown in Figure 1 is recommended. Otherwise, if

multiple bytes in a page or several pages are programmed

randomly in the main memory, then the programming algo-

rithm shown in Figure 2 is recommended.

STATUS REGISTER: The status register can be used to

determine the device’s ready/busy status, the result of a

Main Memory Page to Buffer Compare operation, or the

device density. To read the status register, an opcode of

57H must be loaded into the device. After the last bit of the

opcode is shifted in, the eight bits of the status register,

starting with the MSB (bit 7), will be shifted out on the SO

pin during the next eight clock cycles. The five most-signifi-

cant bits of the status register will contain device informa-

tion, while the remaining three least-significant bits are

reserved for future use and will have undefined values.

After bit 0 of the status register has been shifted out, the

sequence will repeat itself (as long as CS remains low and

SCK is being toggled) starting again with bit 7. The data in

the status register is constantly updated, so each repeating

sequence will output new data.

Ready/busy status is indicated using bit 7 of the status reg-

ister. If bit 7 is a 1, then the device is not busy and is ready

to accept the next command. If bit 7 is a 0, then the device

is in a busy state. The user can continuously poll bit 7 of the

status register by stopping SCK once bit 7 has been output.

The status of bit 7 will continue to be output on the SO pin,

and once the device is no longer busy, the state of SO will

change from 0 to 1. There are six operations which can

cause the device to be in a busy state: Main Memory Page

to Buffer Transfer, Main Memory Page to Buffer Compare,

Buffer to Main Memory Page Program with Built-In Erase,

Buffer to Main Memory Page Program without Built-In

Erase, Main Memory Page Program, and Auto Page

Rewrite.

The result of the most recent Main Memory Page to Buffer

Compare operation is indicated using bit 6 of the status

register. If bit 6 is a 0, then the data in the main memory

page matches the data in the buffer. If bit 6 is a 1, then at

least one bit of the data in the main memory page does not

match the data in the buffer.

The device density is indicated using bits 5, 4, and 3 of the

status register. For the AT45D041, the three bits are 0, 1,

and 1. The decimal value of these three binary bits does

not equate to the device density; the three bits represent a

combinational code relating to differing densities of Serial

DataFlash devices, allowing a total of eight different density

configurations.

Read/Program Mode Summary

The modes listed above can be separated into two groups

— modes which make use of the flash memory array

(Group A) and modes which do not make use of the flash

memory array (Group B).

Group A modes consist of:

1.

Main memory page read

2.

Main memory page to buffer 1 (or 2) transfer

3.

Main memory page to buffer 1 (or 2) compare

4.

Buffer 1 (or 2) to main memory page program with

built-in erase

5.

Buffer 1 (or 2) to main memory page program with-

out built-in erase

6.

Main memory page program

7.

Auto page rewrite

Group B modes consist of:

1.

Buffer 1 (or 2) read

2.

Buffer 1 (or 2) write

3.

Status read

If a Group A mode is in progress (not fully completed) then

another mode in Group A should not be started. However,

during this time in which a Group A mode is in progress,

modes in Group B can be started.

This gives the Serial DataFlash the ability to virtually

accommodate a continuous data stream. While data is

being programmed into main memory from buffer 1, data

can be loaded into buffer 2 (or vice versa). See application

note AN-4 (“Using Atmel’s Serial DataFlash”) for more

details.

Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDY/BUSY

COMP

0

1

1

X

X

X