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AT45DB161-JI Datasheet(PDF) 9 Page - ATMEL Corporation |
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AT45DB161-JI Datasheet(HTML) 9 Page - ATMEL Corporation |
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9 / 20 page  AT45DB161 9 AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3 Waveform 1 – Inactive Clock Polarity Low Waveform 2 – Inactive Clock Polarity High CS SCK SI SO tCSS VALID IN tH tSU tWH tWL tCSH tCS tV HIGH IMPEDANCE VALID OUT tHO tDIS HIGH IMPEDANCE CS SCK SI SO tCSS VALID IN tH tSU tWL tWH tCSH tCS tV HIGH Z VALID OUT tHO tDIS HIGH IMPEDANCE |
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