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DAC8412EPZ Datasheet(PDF) 3 Page - Analog Devices |
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DAC8412EPZ Datasheet(HTML) 3 Page - Analog Devices |
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3 / 20 page  Data Sheet DAC8412/DAC8413 Rev. G | Page 3 of 20 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VDD = +15.0 V, VSS = −15.0 V, VLOGIC = +5.0 V, VREFH = +10.0 V, VREFL = −10.0 V,−40°C ≤ TA ≤ +85°C, unless otherwise noted.1 Table 1. Parameter Symbol Conditions Min Typ Max Unit ACCURACY Integral Nonlinearity Error INL E grade ±0.25 ±0.5 LSB F grade ±1 LSB Differential Nonlinearity Error DNL Monotonic over temperature −1 LSB Min-Scale Error VZSE RL = 2 kΩ ±2 LSB Full-Scale Error VFSE RL = 2 kΩ ±2 LSB Min-Scale Temperature Coefficient TCVZSE RL = 2 kΩ 15 ppm/°C Full-Scale Temperature Coefficient TCVFSE RL = 2 kΩ 20 ppm/°C Linearity Matching Adjacent DAC Matching ±1 LSB REFERENCE Positive Reference Input Voltage Range2 VREFL + 2.5 VDD − 2.5 V Negative Reference Input Voltage Range2 −10 VREFH − 2.5 V Reference High Input Current IREFH −2.75 +1.5 +2.75 mA Reference Low Input Current IREFL −2.75 −2 0 mA Large Signal Bandwidth BW −3 dB, VREFH = 0 V to 10 V p-p 160 kHz AMPLIFIER CHARACTERISTICS Output Current IOUT RL = 2 kΩ, CL = 100 pF –5 +5 mA Settling Time tS To 0.01%, 10 V step, RL = 1 kΩ 10 μs Slew Rate SR 10% to 90% 2.2 V/μs Analog Crosstalk 72 dB LOGIC CHARACTERISTICS Logic Input High Voltage VINH TA = 25°C 2.4 V Logic Input Low Voltage VINL TA = 25°C 0.8 V Logic Output High Voltage VOH IOH = 0.4 mA 2.4 V Logic Output Low Voltage VOL IOL = −1.6 mA 0.4 V Logic Input Current IIN 1 μA Input Capacitance CIN 8 pF Digital Feedthrough3 VREFH = 2.5 V, VREFL = 0 V 5 nV-sec LOGIC TIMING CHARACTERISTICS3, 4 Chip Select Write Pulse Width tWCS 80 ns Write Setup tWS tWCS = 80 ns 0 ns Write Hold tWH tWCS = 80 ns 0 ns Address Setup tAS 0 ns Address Hold tAH 0 ns Load Setup tLS 70 ns Load Hold tLH 30 ns Write Data Setup tWDS tWCS = 80 ns 20 ns Write Data Hold tWDH tWCS = 80 ns 0 ns Load Data Pulse Width tLDW 170 ns Reset Pulse Width tRESET 140 ns Chip Select Read Pulse Width tRCS 130 ns Read Data Hold tRDH tRCS = 130 ns 0 ns Read Data Setup tRDS tRCS = 130 ns 0 ns Data to High-Z tDZ CL = 10 pF 200 ns Chip Select to Data tCSD CL = 100 pF 160 ns |
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