ADF7902

Rev. 0 | Page 9 of 12

TEST MODES

If CLKOUT_ENB is tied high, CLKOUT is disabled. The

CLKOUT pin is reconfigured as a test enable input. If the

CLKOUT pin is then tied low, the part operates as is normal

with CLKOUT off. If it is tied high (2.2 V), the part is in test

mode. Test mode is described in Table 5.

When CLKOUT_ENB = 0, RSSI appears on the test output pin

(Pin 2), and CLKOUT is configured as an output with a 9.8 MHz

clock coming out.

When test mode is enabled, the channel frequency is set to

369.5 MHz (Channel 1).

Table 5. Test Modes

CH1_SEL

CH2_SEL

CH3_SEL

Test Mode

0

0

0

agc gain is set to maximum (filti is also set to maximum on test output pin)

0

0

1

filti on test output pin

0

1

0

filtq on test output pin

0

1

1

Charge pump output is set to maximum (test pin is also tri-state)

1

0

0

Charge pump output is set to minimum (also n-divider output ÷ 2 on test output pin)

1

0

1

Charge pump is tri-state (test pin is also tri-state)

1

1

0

n-divider output ÷ 2 on test output pin

1

1

1

Recovered data clock on test output pin