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ATF1500ABV-12JC Datasheet(PDF) 4 Page - ATMEL Corporation

Part # ATF1500ABV-12JC
Description  High- Performance EE PLD
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATF1500ABV-12JC Datasheet(HTML) 4 Page - ATMEL Corporation

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ATF1500ABV/L
4
ATF1500ABV Macrocell
ATF1500ABV Macrocell
The ATF1500ABV macrocell is flexible enough to support
highly complex logic functions operating at high speed. The
macrocell consists of five sections: product terms and prod-
uct term select multiplexer; OR/XOR/CASCADE logic; a flip
flop; output select and enable; and logic array inputs.
Product Terms and Select Mux
Each ATF1500ABV macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1500ABV macrocell's OR/XOR/CASCADE logic
structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be
routed to the OR gate, creating a five input AND/OR sum
term. With the addition of the CASIN from neighboring
macrocells, this can be expanded to as many as 40 product
terms with a very small additional delay.
The macrocell's XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows output polarity
selection. For registered functions, the fixed levels allow De
Morgan minimization of the product terms. The XOR gate is
also used to emulate JK type flip flops.
Flip Flop
The ATF1500ABV’s flip flop has very flexible data and con-
trol functions. The data input can come from either the XOR
gate or from a separate product term. Selecting the sepa-
rate product term allows creation of a buried registered
feedback within a combinatorial output macrocell.
In addition to D, T, JK and SR operation, the flip flop can
also be configured as a flow-through latch. In this mode,


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