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ATF1500ABV-15AI Datasheet(PDF) 5 Page - ATMEL Corporation

Part # ATF1500ABV-15AI
Description  High- Performance EE PLD
Download  12 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATF1500ABV-15AI Datasheet(HTML) 5 Page - ATMEL Corporation

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ATF1500ABV/L
5
data passes through when the clock is high and is latched
when the clock is low.
The clock itself can be either the global CLK pin or an indi-
vidual product term. The flip flop changes state on the
clock's rising edge. When the CLK pin is used as the clock,
one of the macrocell product terms can be selected as a
clock enable. When the clock enable function is active and
the enable signal (product term) is low, all clock edges are
ignored.
The flip flop's asynchronous reset signal (AR) can be either
the pin global clear (GCLR), a product term, or always off.
AR can also be a logic OR of GCLR with a product term.
The asynchronous preset (AP) can be a product term or
always off.
Output Select and Enable
The ATF1500ABV macrocell output can be selected as
registered or combinatorial. When the output is registered,
the same registered signal is fed back internally to the glo-
bal bus. When the output is combinatorial, the buried feed-
back can be either the same combinatorial signal or it can
be the register output if the separate product term is cho-
sen as the flip flop input.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available, includ-
ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can also be selected
as either of the two OE pins or as an individual product
term.
Global/Regional Busses
The global bus contains all Input and I/O pin signals as well
as the buried feedback signal from all 32 macrocells.
Together with the complement of each signal, this provides
a 68-bit bus as input to every product term. Having the
entire global bus available to each macrocell eliminates any
potential routing problems. With this architecture designs
can be modified without requiring pinout changes.
Each macrocell also generates a foldback product term.
This signal goes to the regional bus, and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell's product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with a small additional delay.


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