AT89C51

4-33

Power Down Mode

In the power down mode the oscillator is stopped, and the

instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Regis-

ters retain their values until the power down mode is termi-

nated. The only exit from power down is a hardware reset.

Reset redefines the SFRs but does not change the on-chip

restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and sta-

bilize.

Program Memory Lock Bits

On the chip are three lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the table below:

When lock bit 1 is programmed, the logic level at the EA pin

is sampled and latched during reset. If the device is pow-

ered up without a reset, the latch initializes to a random

value, and holds that value until reset is activated. It is nec-

essary that the latched value of EA be in agreement with

the current logic level at that pin in order for the device to

function properly.

Lock Bit Protection Modes

Program Lock Bits

Protection Type

LB1

LB2

LB3

1

U

U

U

No program lock features.

2

P

U

U

MOVC instructions executed from external program memory are disabled from fetching code

bytes from internal memory, EA is sampled and latched on reset, and further programming of the

Flash is disabled.

3

P

P

U

Same as mode 2, also verify is disabled.

4

P

P

P

Same as mode 3, also external execution is disabled.

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash

memory array in the erased state (that is, contents = FFH)

and ready to be programmed. The programming interface

accepts either a high-voltage (12-volt) or a low-voltage

ming mode provides a convenient way to program the

AT89C51 inside the user’s system, while the high-voltage

programming mode is compatible with conventional third

party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or

low-voltage programming mode enabled. The respective

top-side marking and device signature codes are listed in

the following table.

The AT89C51 code memory array is programmed byte-by-

byte in either programming mode.

To program any non-

blank byte in the on-chip Flash Memory, the entire memory

must be erased using the Chip Erase Mode.

Programming Algorithm: Before programming the

AT89C51, the address, data and control signals should be

set up according to the Flash programming mode table and

Figures 3 and 4. To program the AT89C51, take the follow-

ing steps.

1.

Input the desired memory location on the address

lines.

2.

Input the appropriate data byte on the data lines.

3.

Activate the correct combination of control signals.

4.

mode.

5.

Pulse ALE/PROG once to program a byte in the Flash

array or the lock bits. The byte-write cycle is self-timed

and typically takes no more than 1.5 ms. Repeat steps

1 through 5, changing the address and data for the

entire array or until the end of the object file is reached.

Data Polling: The AT89C51 features Data Polling to indi-

cate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written datum on PO.7. Once the write cycle

has been completed, true data are valid on all outputs, and

the next cycle may begin. Data Polling may begin any time

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also

be monitored by the RDY/BSY output signal. P3.4 is pulled

low after ALE goes high during programming to indicate

BUSY. P3.4 is pulled high again when programming is

done to indicate READY.

Top-Side Mark

AT89C51

xxxx

yyww

AT89C51

xxxx-5

yyww

Signature

(030H)=1EH

(031H)=51H

(032H)=FFH

(030H)=1EH

(031H)=51H

(032H)=05H