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ATF1502AS-15JC44 Datasheet(PDF) 6 Page - ATMEL Corporation |
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ATF1502AS-15JC44 Datasheet(HTML) 6 Page - ATMEL Corporation |
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6 / 18 page  ATF1502AS 6 JTAG-BST/ISP Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1502AS. The boundary-scan technique involves the inclusion of a shift- register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component bound- aries can be controlled and observed using scan testing methods. Each input pin and I/O pin has its own boundary scan cell (BSC) to support boundary scan testing. The ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power up. The five JTAG modes supported include: SAM- PLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows ATF1502AS programming to be described and imple- mented using any one of the 3rd party development tools supporting this standard. The ATF1502AS has the option of using four JTAG-stan- dard I/O pins for boundary scan testing (BST) and in-sys- tem programming (ISP) purposes. The ATF1502AS is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. JTAG Boundary Scan Cell (BSC) Testing The ATF1502AS contains up to 32 I/O pins and 4 input pins, depending on the and package type selected. Each input pin and I/O pin has its own boundary scan cell (BSC) in order to support boundary scan testing as described in detail by IEEE Standard 1149.1. Typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture regis- ters. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below. BSC Configuration for Input and I/O Pins (except JTAG TAP Pins) Note: The ATF1502AS has pull-up option on TMS and TDI pins. This feature is selected as a design option. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Case) 0 °C - 70°C-40°C - 85°C V CCINT or VCCIO (5V) Power Supply 5V ± 5% 5V ± 10% V CCIO (3.3V) Power Supply 3.0V - 3.6V 3.0V - 3.6V |
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