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ATF20V8B-7JC Datasheet(PDF) 5 Page - ATMEL Corporation |
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ATF20V8B-7JC Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 17 page ATF20V8B 5 Input Test Waveforms and Measurement Levels t R, tF < 5 ns (10% to 90%) Output Test Loads Commercial Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Up Reset The registers in the ATF20V8Bs are designed to reset dur- ing power up. At a point delayed slightly from V CC crossing V RST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up. This feature is critical for state machine initialization. How- ever, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the fol- lowing conditions are required: 1. The V CC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during t PR. Preload of Registered Outputs The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF20V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Programming/Erasing Programming/erasing is performed using standard PLD programmers. For further information, see the Configurable Logic Databook, section titled, “CMOS PLD Programming Hardware and Software Support.” Pin Capacitance f = 1 MHz, T = 25°C (1) Typ Max Units Conditions C IN 58 pF V IN = 0V C OUT 68 pF V OUT = 0V Parameter Description Typ Max Units t PR Power-Up Reset Time 600 1,000 ns V RST Power-Up Reset Voltage 3.8 4.5 V |
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