AT93C46/56/57/66

6

Functional Description

The AT93C46/56/57/66 is accessed via a simple and ver-

satile 3-wire serial communication interface. Device opera-

tion is controlled by seven instructions issued by the host

processor. A valid instruction starts with a rising edge

of CS and consists of a Start Bit (logic ‘1’) followed by the

appropriate Op Code and the desired memory Address

location.

READ (READ):

The Read (READ) instruction contains

the Address code for the memory location to be read. After

the instruction and address are decoded, data from the

selected memory location is available at the serial output

pin DO. Output data changes are synchronized with the ris-

ing edges of serial clock SK. It should be noted that a

dummy bit (logic ‘0’) precedes the 8- or 16-bit data output

string.

ERASE/WRITE (EWEN):

To assure data integrity, the

part automatically goes into the Erase/Write Disable

(EWDS) state when power is first applied. An Erase/Write

Enable (EWEN) instruction must be executed first before

any programming instructions can be carried out. Please

note that once in the Erase/Write Enable state, program-

ming remains enabled until an Erase/Write Disable

from the part.

ERASE (ERASE):

The Erase (ERASE) instruction pro-

grams all bits in the specified memory location to the logical

‘1’ state. The self-timed erase cycle starts once the ERASE

instruction and address are decoded. The DO pin outputs

the READY/BUSY status of the part if CS is brought high

‘1’ at pin DO indicates that the selected memory location

has been erased, and the part is ready for another instruc-

tion.

WRITE (WRITE):

The Write (WRITE) instruction contains

the 8 or 16 bits of data to be written into the specified mem-

ory location. The self-timed programming cycle, t

after the last bit of data is received at serial data input pin

DI. The DO pin outputs the READY/BUSY status of the part

if CS is brought high after being kept low for a minimum of

250 ns (t

still in progress. A logic ‘1’ indicates that the memory loca-

tion at the specified address has been written with the data

pattern contained in the instruction and the part is ready for

further instructions. A READY/BUSY status cannot be

obtained if the CS is brought high after the end of the

self-timed programming cycle, t

ERASE ALL (ERAL):

The Erase All (ERAL) instruction

programs every bit in the memory array to the logic ‘1’ state

and is primarily used for testing purposes. The DO pin out-

puts the READY/BUSY status of the part if CS is brought

ERAL instruction is valid only at V

WRITE ALL (WRAL):

The Write All (WRAL) instruction

programs all memory locations with the data patterns spec-

ifi ed in the ins t r u c t ion . The DO pi n ou tputs th e

READY/BUSY status of the part if CS is brought high after

instruction is valid only at V

ERASE/WRITE DISABLE (EWDS):

To protect against

accidental data disturb, the Erase/Write Disable (EWDS)

instruction disables all programming modes and should be

executed after all programming operations. The operation

of the READ instruction is independent of both the EWEN

and EWDS instructions and can be executed at any time.

Instruction Set for the AT93C56 and AT93C66

Instruction

SB

Op

Code

Address

Data

Comments

x 8

x 16

x 8

x 16

READ

1

10

A

A

Reads data stored in memory, at

specified address.

EWEN

1

00

11XXXXXXX

11XXXXXX

Write enable must precede all

programming modes.

ERASE

1

11

A

A

Erases memory location A

WRITE

1

01

A

A

D

D

Writes memory location A

ERAL

1

00

10XXXXXXX

10XXXXXX

Erases all memory locations. Valid

only at V

WRAL

1

00

01XXXXXXX

01XXXXXX

D

D

Writes all memory locations. Valid

when V

Register cleared.

EWDS

1

00

00XXXXXXX

00XXXXXX

Disables all programming instructions.