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ATF1502AS-15JI44 Datasheet(PDF) 3 Page - ATMEL Corporation |
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ATF1502AS-15JI44 Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 18 page ATF1502AS 3 Each macrocell also generates a foldback logic term, which goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast, efficient generation of com- plex logic functions. The ATF1502AS contains four such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms. The ATF1502AS macrocell shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, w hen p r o g r ammed , pr ot ects t he cont ent s of t h e ATF1502AS. Two bytes (16-bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse. The ATF1502AS device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Figure 1. ATF1502AS Macrocell Product Terms and Select MUX Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is deter- mined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/CASCADE Logic The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5- input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinato- rial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. Flip Flop The ATF1502AS’s flip flop has very flexible data and con- trol functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output |
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