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AT6005-4AI Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT6005-4AI Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 28 page  AT6000(LV) Series 5 In addition to the four local-bus connections, a cell receives two inputs and p rovides two outputs to ea ch of its North (N), South (S), East (E) and West (W) neighbors. These inputs and outputs are divided into two classes: “A” and “B”. There is an A input and a B input from each neigh- boring cell and an A output and a B output driving all four neighbors. Between cells, an A output is always connected to an A input and a B output to a B input. Within the cell, the four A inputs and the four B inputs enter two separate, independently configurable multiplexers. Cell flexibility is enhanced by allowing each multiplexer to select also the logical constant “1”. The two multiplexer outputs enter the two upstream AND gates. Downstream from these two AND gates are an Exclusive- OR (XOR) gate, a register, an AND gate, an inverter and two four-input multiplexers producing the A and B outputs. These multiplexers are controlled in tandem (unlike the A and B input multiplexers) and determine the function of the cell. • In State 0 – corresponding to the “0” inputs of the multiplexers – the output of the left-hand upstream AND gate is connected to the cell’s A output, and the output of the right-hand upstream AND gate is connected to the cell’s B output. • In State 1 – corresponding to the “1” inputs of the multiplexers – the output of the left-hand upstream AND gate is connected to the cell’s B output, the output of the right-hand upstream AND gate is connected to the cell’s A output. • In State 2 – corresponding to the “2” inputs of the multiplexers – the XOR of the outputs from the two upstream AND gates is provided to the cell’s A output, while the NAND of these two outputs is provided to the cell’s B output. • In State 3 – corresponding to the “3” inputs of the multiplexers – the XOR function of State 2 is provided to the D input of a D-type flip-flop, the Q output of which is connected to the cell’s A output. Clock and asynchronous reset signals are supplied externally as described later. The AND of the outputs from the two upstream AND gates is provided to the cell's B output. Logic States The Atmel cell implements a rich and powerful set of logic functions, stemming from 44 logical cell states which per- mutate into 72 physical states. Some states use both A and B inputs. Other states are created by selecting the “1” input on either or both of the input multiplexers. There are 28 combinatorial primitives created from the cell’s tristate capabilities and the 20 physical states repre- sented in Figure 5. Five logical primitives are derived from the physical constants shown in Figure 7. More complex functions are created by using cells in combination. A two-input AND feeding an XOR (Figure 8) is produced using a single cell (Figure 9). A two-to-one multiplexer selects the logical constant “0” and feeds it to the right- hand AND gate. The AND gate acts as a feed-through, let- ting the B input pass through to the XOR. The three-to-one multiplexer on the right side selects the local-bus input, LNS1, and passes it to the left-hand AND gate. The A and LNS1 signals are the inputs to the AND gate. The output of the AND gate feeds into the XOR, producing the logic state (AlL) XOR B. |
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