Registered Output Preload

The ATF16V8CZ’s registers are provided with circuitry to

allow loading of each register with either a high or a low.

This feature will simplify testing since any state can be

forced into the registers to control test sequencing. A

JEDEC file with preload is generated when a source file

with vectors is compiled. Once downloaded, the JEDEC

file preload sequence will be done automatically by ap-

proved programmers.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying

of the ATF16V8CZ fuse patterns. Once programmed, fuse

verify and preload are inhibited. However, the 64-bit User

Signature remains accessible.

The security fuse should be programmed last, as its effect

is immediate.

Input and I/O Pin Keeper Circuits

The ATF16V8CZ contains internal input and I/O pin

keeper circuits. These circuits allow each ATF16V8CZ pin

to hold its previous value even when it is not being driven

by an external source or by the device’s output buffer. This

helps insure that all logic array inputs are at known, valid

logic levels. This reduces system power by preventing

pins from floating to indeterminate levels. By using pin

keeper circuits rather than pull-up resistors, there is no DC

current required to hold the pins in either logic state (high

or low).

These pin keeper circuits are implemented as weak feed-

back inverters, as shown in the Input Diagram below.

These keeper circuits can easily be overdriven by stand-

ard TTL- or CMOS-compatible drivers. The typical over-

drive current required is 40

µA.

Input Diagram

I/O Diagram

Compiler Mode Selection

Registered

Complex

Simple

Auto Select

ABEL, Atmel-ABEL

P16V8R

P16V8C

P16V8AS

P16V8

CUPL

G16V8MS

G16V8MA

G16V8AS

G16V8A

LOG/iC

GAL16V8

OrCAD-PLD

“Registered”

“Complex”

“Simple”

GAL16V8A

PLDesigner

P16V8R

P16V8C

P16V8C

P16V8A

Tango-PLD

G16V8R

G16V8C

G16V8AS

G16V8

Note:

1. Only applicable for version 3.4 or lower.

6

ATF16V8CZ