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TRF4400PWG4 Datasheet(PDF) 8 Page - Texas Instruments |
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TRF4400PWG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 21 page TRF4400 SINGLECHIP 433MHz RF TRANSMITTER SLWS113D −NOVEMBER 2000 − REVISED FEBRUARY 2005 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 direct digital synthesizer general principles of DDS operation In general, a direct digital synthesizer (DDS) is based on the principle of generating a sinewave signal in the digital domain. Benefits include high precision, wide frequency range, a high degree of software programmability, and extremely fast lock times. Figure 4 shows a block diagram of a typical DDS. It generally consists of an accumulator, sine lookup table, a digital-to-analog converter, and a low-pass filter. All digital blocks are clocked by the reference oscillator. Synthesizer Frequency Register N-Bit Register + Sine Lookup Table DAC Low-Pass Filter Analog Output Signal Load With Frequency Word Figure 4. Typical DDS Block Diagram The DDS constructs an analog sine waveform using an N-bit adder counting up from 0 to 2N in steps of the frequency register whereby generating a digital ramp waveform. Each number in the N-bit output register is used to select the corresponding sine wave value out of the sine lookup table. After the digital-to-analog conversion, a low-pass filter is necessary to suppress unwanted spurious responses. The analog output signal can be used as a reference input signal for a phase-locked loop (PLL). The PLL circuit multiplies the reference frequency by a predefined factor. TRF4400 direct digital synthesizer implementation Figure 5 shows a block diagram of the DDS implemented in the TRF4400. It consists of a 24-bit accumulator clocked by the reference oscillator along with control logic settings. DDS Mode0 Frequency Setting Mode0/1 Select Logic 24-Bit Register DDS Frequency Register Modulation Control Logic 22 22 24 8 + + 24 11 11-Bit DAC Sine Shaper Low-pass Filter TX_DATA − (Terminal 14) C − Word / MM Bit (Modulation Mode Select) ƒDDS to PLL FSK Frequency Deviation Register D − Word / DEV Bits (FSK Deviation) A − Word MODE − (Terminal 11) B − Word DDS Mode1 Frequency Setting Reference Frequency, ƒref Figure 5. DDS Block Diagram as Implemented in the TRF4400 |
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