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ATV2500B-15LM Datasheet(PDF) 10 Page - ATMEL Corporation |
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ATV2500B-15LM Datasheet(HTML) 10 Page - ATMEL Corporation |
10 / 18 page ATV2500B 10 Power-Up Reset The registers in the ATV2500Bs are designed to reset dur- ing power up. At a point delayed slightly from V CC crossing V RST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the fol- lowing conditions are required: 1. The V CC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. The clock pin, and any signals from which clock terms are derived, must remain stable during t PR. Level forced on Odd I/O pin during PRELOAD cycle Q Select Pin State Even/Odd Select Even Q1 state after cycle Even Q2 state after cycle Odd Q1 state after cycle Odd Q2 state after cycle V IH/VIL Low Low High/Low X X X V IH/VIL High Low X High/Low X X V IH/VIL Low High X X High/Low X V IH/VIL High High X X X High/Low Parameter Description Typ Max Units t PR Power-Up Reset Time 600 1000 ns V RST Power-Up Reset Voltage 3.8 4.5 V |
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