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ATF1504ASZ-20JC68 Datasheet(PDF) 4 Page - ATMEL Corporation |
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ATF1504ASZ-20JC68 Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 21 page  ATF1504ASZ 4 TTL, SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices increase usable gate count, and the odds of successful pin-locked design modifi- cations. The ATF1504AS has up to 68 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device pack- age selected. Each dedicated pin can also serve as a glo- bal control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 64 macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term, which goes to a regional bus. Cascade logic between macrocells in the ATF1504AS allows fast, efficient generation of com- plex logic functions. The ATF1504AS contains four such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms. The ATF1504AS macrocell shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs. Block Diagram Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, w hen p r o g r ammed , pr ot ects th e cont ents o f th e ATF1504AS. Two bytes (16-bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse. The ATF1504AS device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. |
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