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ATV2500BL-20KM Datasheet(PDF) 3 Page - ATMEL Corporation |
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ATV2500BL-20KM Datasheet(HTML) 3 Page - ATMEL Corporation |
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3 / 18 page  ATV2500B 3 Description The ATV2500Bs are the highest density PLDs available in a 40- or 44-pin package. With their fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATV2500Bs are organized around a single universal and-or array. All pin and feedback terms are always avail- able to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATV2500Bs, four product terms are input to each sum term. Furthermore, each macrocell's three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individu- ally configured to have direct input pin clocking. Each out- put has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power up. Several low power device options allow selection of the optimum solution for many power-sensitive applications. Each of the options significantly reduces total system power and enhances system reliability. Functional Logic Diagram Description The ATV2500B functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the sin- gle global bus. The ATV2500Bs are straightforward and uniform PLDs. The 24 macrocells are numbered 0 through 23. Each mac- rocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed in a 2/4 pat- tern. The first four macrocells share Preset 0, the next two share Preset 1, and so on, ending with the last two macro- cells sharing Preset 7. The 14 dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2 (1) true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell. Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATV2500Bs. |
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