1

Features

– Easily Achieves Gate Utilization Factors of 80 Percent

– 86 Inputs and 72 Sum Terms

– 48 Flip-Flops - 2 per Macrocell

– 3 Sum Terms - Can Be OR'ed and Shared

and I/O Bus Compatibility

– Multiple Synchronous Presets - One per Four or Eight Flip-Flops

– 2000V ESD Protection

– 200 mA Latchup Immunity

Block Diagram

Description

The ATV2500H/L is the most powerful programmable logic device available in a 40-

pin package. Increased product terms, sum terms, and flip-flops translate into many

more usable gates. High gate utilization is easily obtainable.

The ATV2500H/L is organized around a global bus. All pin and feedback terms are

always available to every logic cell. Each of the 38 logic pins and their complements

are array inputs, as well as the true and false outputs of each of the 48 flip-flops.

High-Density

UV-Erasable

Programmable

Logic Device

ATV2500H

ATV2500L

Rev. 0025E–05/98

(continued)

Pin Configurations

Pin Name

Function

IN

Logic Inputs

I/O

Bidirectional Buffers

I/O, 0,2,4..

“Even” I/O Buffers

I/O, 1,3,5..

“Odd” I/O Buffers

*

No Internal Connection

VCC

+5V Supply

DIP

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

IN

IN

IN

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

VCC

I/O17

I/O16

I/O15

I/O14

I/O13

I/O12

IN

IN

IN

IN

IN

IN

IN

IN

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

GND

I/O23

I/O22

I/O21

I/O20

I/O19

I/O18

IN

IN

IN

PLCC/LCC

* = No Connect

7

8

9

10

11

12

13

14

15

16

17

39

38

37

36

35

34

33

32

31

30

29

I/O2

I/O3

I/O4

I/O5

VCC

VCC

I/O17

I/O16

I/O15

I/O14

I/O13

I/O7

I/O8

I/O9

I/O10

I/O11

GND

GND

I/O23

I/O22

I/O21

I/O20