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TS68020MF20 Datasheet(PDF) 5 Page - ATMEL Corporation |
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TS68020MF20 Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 45 page 5 TS68020 2115A–HIREL–07/02 Table 1. Signal Index Signal Name Mnemonic Function Address Bus A0-A31 32-bit Address Bus Used to address any of 4, 294, 967, 296 bytes. Data Bus D0-D31 32-bit Data Bus Used to Transfer 8, 16, 24 or 32 bits of Data Per Bus Cycle. Function Codes FC0-FC2 3-bit Function Case Used to Identify the Address Space of Each Bus Cycle. Size SIZ0/SIZ1 Indicates the Number of Bytes Remaining to be Transferred for this Cycle. These Signals, Together with A0 And A1, Define the Active Sections of the Data Bus. Read-Modify-Write Cycle RMC Provides an Indicator that the Current Bus Cycle is Part of an Indivisibleread- modify-write Operation. External Cycle Start ECS Provides an Indication that a Bus Cycle is Beginning. Operand Cycle Start OCS Identical Operation to that of ECS Except that OCS Is Asserted Only During the First Bus Cycle of an Operand Transfer. Address Strobe AS Indicates that a Valid Address is on The Bus. Data Strobe DS Indicates that Valid Data is to be Placed on the Data Bus by an External Device or has been Laced on the Data Bus by the TS68020. Read/Write R/W Defines the Bus Transfer as an MPU Read or Write. Data Buffer Enable DBEN Provides an Enable Signal for External Data Buffers. Data Transfer and Size Acknowledge DSACK0/DSACK1 Bus Response Signals that Indicate the Requested Data Transfer Operation is Completed. In Addition, these Two Lines Indicate the Size of the External Bus Port on a Cycle-by-cycle Basis. Cache Disable CDIS Dynamically Disables the On-chip Cache to Assist Emulator Support. Interrupt Priority Level IPL0-IPL2 Provides an Encoded Interrupt Level to the Processor. Autovector AVEC Requests an Autovector During an Interrupt Acknowledge Cycle. Interrupt Pending IPEND Indicates that an Interrupt is Pending. Bus Request BR Indicates that an External Device Requires Bus Mastership. Bus Grant BG Indicates that an External Device may Assume Bus Mastership. Bus Grant Acknowledge BGACK Indicates that an External Device has Assumed Bus Mastership. Reset RESET System Reset. Halt HALT Indicates that the Processor Should Suspend Bus Activity. Bus Error BERR Indicates an Invalid or Illegal Bus Operation is Being Attempted. Clock CLK Clock Input to the Processor. Power Supply VCC +5-volt ± 10% Power Supply. Ground GND Ground Connection. |
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