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LTC1068-50CG-PBF Datasheet(PDF) 6 Page - Linear Technology

Part # LTC1068-50CG-PBF
Description  Clock-Tunable, Quad Second Order, Filter Building Blocks
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1068-50CG-PBF Datasheet(HTML) 6 Page - Linear Technology

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LTC1068 Series
6
1068fc
ELECTRICAL CHARACTERISTICS LTC1068-25 (Internal Op Amps). The
l
denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Supply Voltage Range
3.14
±5.5
V
Voltage Swings
VS = 3.14V, RL = 5k (Note 2)
VS = 4.75V, RL = 5k (Note 3)
VS = ±5V, RL = 5k
l
l
l
1.2
2.6
±3.4
1.6
3.4
±4.1
VP-P
VP-P
V
Output Short-Circuit Current (Source/Sink)
VS = ±4.75V
VS = ±5V
17/6
20/15
mA
mA
DC Open-Loop Gain
RL = 5k
85
dB
GBW Product
VS = ±5V
6
MHz
Slew Rate
VS = ±5V
10
V/µs
Analog Ground Voltage (Note 4)
VS = 5V, Voltage at AGND
2.5V ±2%
V
LTC1068-25 (Complete Filter) VS = ±5V, TA = 25°V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Clock-to-Center Frequency Ratio (Note 5)
VS = 4.75V, fCLK = 500kHz, Mode 1 (Note 3),
fO = 20kHz, Q = 5, VIN = 0.5VRMS,
R1 = R3 = 49.9k, R2 = 10k
l
25 ±0.3
25 ±0.8
25 ±0.9
%
%
VS = ±5V, fCLK = 1MHz, Mode 1,
fO = 40kHz, Q = 5, VIN = 1VRMS,
R1 = R3 = 49.9k, R2 = 10k
l
25 ±0.3
25 ±0.8
25 ±0.9
%
%
Clock-to-Center Frequency Ratio,
Side-to-Side Matching (Note 5)
VS = 4.75V, fCLK = 500kHz, Q = 5 (Note 3)
VS = ±5V, fCLK = 1MHz, Q = 5
l
l
±0.25
±0.25
±0.9
±0.9
%
%
Q Accuracy (Note 5)
VS = 4.75V, fCLK = 500kHz, Q = 5 (Note 3)
VS = ±5V, fCLK = 1MHz, Q = 5
l
l
±1
±1
±3
±3
%
%
fO Temperature Coefficient
±1
ppm/°C
Q Temperature Coefficient
±5
ppm/°C
DC Offset Voltage (Note 5)
(See Table 1)
VS = ±5V, fCLK = 1MHz, VOS1
(DC Offset of Input Inverter)
l
0
±15
mV
VS = ±5V, fCLK = 1MHz, VOS2
(DC Offset of First Integrator)
l
–2
±25
mV
VS = ±5V, fCLK = 1MHz, VOS3
(DC Offset of Second Integrator)
l
–5
±40
mV
Clock Feedthrough
VS = ±5V, fCLK = 1MHz
0.25
mVRMS
Max Clock Frequency (Note 6)
VS = ±5V, Q ≤ 1.6, Mode 1
5.6
MHz
Power Supply Current
VS = 3.14V, fCLK = 1MHz (Note 2)
VS = 4.75V, fCLK = 1MHz (Note 3)
VS = ±5V, fCLK = 1MHz
l
l
l
3.5
6.5
9.5
8
11
15
mA
mA
mA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Production testing for single 3.14V supply is achieved by using
the equivalent dual supplies of ±1.57V.
Note 3: Production testing for single 4.75V supply is achieved by
using the equivalent dual supplies of ±2.375V.
Note 4: Pin 7 (AGND) is the internal analog ground of the device. For
single supply applications this pin should be bypassed with a 1µF
capacitor. The biasing voltage of AGND is set with an internal resistive
divider from Pin 8 to Pin 23 (see Block Diagram).
Note 5: Side D is guaranteed by design.
Note 6: See Typical Performance Characteristics.


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