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LTC1605CSW Datasheet(PDF) 7 Page - Linear Technology

Part # LTC1605CSW
Description  16-Bit, 100ksps, Sampling ADC
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1605CSW Datasheet(HTML) 7 Page - Linear Technology

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7
1605fc
LTC1605
PIN FUNCTIONS
on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on
Pin 6 and the LSB is output on Pin 13.
R/C (Pin 24): Read/Convert Input. With CS low, a falling
edge on R/C puts the internal sample-and-hold into the
hold state and starts a conversion. With CS low, a rising
edge on R/C enables the output data bits.
CS (Pin 25): Chip Select. Internally OR’d with R/C. With
R/C low, a falling edge on CS will initiate a conversion.
With R/C high, a falling edge on CS will enable the output
data.
BUSY (Pin 26): Output Shows Converter Status. It is low
when a conversion is in progress. Data valid on the rising
edge of BUSY. CS or R/C must be high when BUSY rises
or another conversion will start without time for signal
acquisition.
VANA (Pin 27): 5V Analog Supply. Bypass to ground with
a 0.1
µF ceramic and a 10µF tantalum capacitor.
VDIG (Pin 28): 5V Digital Supply. Connect directly to Pin
27.
TEST CIRCUITS
Load Circuit for Access Timing
1k
CL
CL
DBN
DBN
1k
5V
LTC1605 • TC01
A. HI-Z TO VOH AND VOL TO VOH
B. HI-Z TO VOL AND VOH TO VOL
Load Circuit for Output Float Delay
1k
50pF
50pF
DBN
DBN
1k
5V
LTC1605 • TC02
A. VOH TO HI-Z
B. VOL TO HI-Z
FUNCTIONAL BLOCK DIAGRA
16-BIT CAPACITIVE DAC
COMP
REF BUF
2.5V REF
CAP
(2.5V)
CSAMPLE
CSAMPLE
D15
D0
BUSY
CONTROL LOGIC
R/C
BYTE
INTERNAL
CLOCK
CS
ZEROING SWITCHES
VDIG
VANA
VIN
REF
AGND1
AGND2
DGND
16
LTC1605 • BD
+
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
4k
20k
4k
10k


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