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7C372I-100 Datasheet(PDF) 6 Page - Cypress Semiconductor |
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7C372I-100 Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 13 page  CY7C372i Document #: 38-03033 Rev. *A Page 6 of 13 Switching Characteristics Over the Operating Range [14] Parameter Description 7C372i-125 7C372i-100 7C372i-83 7C372iL-83 7C372i-66 7C372iL-66 Unit Min. Max. Min. Max. Min. Max. Min. Max. Combinatorial Mode Parameters tPD Input to Combinatorial Output[1] 10 12 15 20 ns tPDL Input to Output Through Transparent Input or Output Latch[1] 13 15 18 22 ns tPDLL Input to Output Through Transparent Input and Output Latches[1] 15 16 19 24 ns tEA Input to Output Enable[1] 14 16 19 24 ns tER Input to Output Disable 14 16 19 24 ns Input Registered/Latched Mode Parameters tWL Clock or Latch Enable Input LOW Time[9] 33 4 5 ns tWH Clock or Latch Enable Input HIGH Time[9] 33 4 5 ns tIS Input Register or Latch Set-Up Time 2 2 3 4 ns tIH Input Register or Latch Hold Time 2 2 3 4 ns tICO Input Register Clock or Latch Enable to Combinatorial Output[1] 14 16 19 24 ns tICOL Input Register Clock or Latch Enable to Output Through Transparent Output Latch[1] 16 18 21 26 ns Output Registered/Latched Mode Parameters tCO Clock or Latch Enable to Output[1] 6.5 6.5 8 10 ns tS Set-Up Time from Input to Clock or Latch Enable 5.5 6 8 10 ns tH Register or Latch Data Hold Time 0 0 0 0 ns tCO2 Output Clock or Latch Enable to Output Delay (Through Memory Array)[1] 14 16 19 24 ns tSCS Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) 810 12 15 ns tSL Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable 10 12 15 20 ns tHL Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable 00 0 0 ns fMAX1 Maximum Frequency with Internal Feedback in Output Registered Mode (Least of 1/tSCS, 1/(tS + tH), or 1/tCO) [9] 125 100 83 66 MHz fMAX2 Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO) [9] 153.8 153.8 125 100 MHz fMAX3 Maximum Frequency with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH)) [9] 83.3 80 62.5 50 MHz tOH-tIH 37x Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[9, 15] 00 0 0 ns Pipelined Mode Parameters tICS Input Register Clock to Output Register Clock 8 10 12 15 ns fMAX4 Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS) [9] 125 100 83.3 66.6 MHz Notes: 14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C372i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. |
Similar Part No. - 7C372I-100 |
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Similar Description - 7C372I-100 |
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