CY14B104NA-BA45XI datasheet(4/26 Pages) CYPRESS

Part #	CY14B104NA-BA45XI

Description	4-Mbit (512 K x 8/256 K x 16) nvSRAM

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY14B104LA, CY14B104NA

Document Number: 001-49918 Rev. *M

Page 4 of 26

Figure 3. Pin Diagram – 54-pin TSOP II pinout

Pinouts (continued)

A17

DQ7

DQ6

DQ5

DQ4

VCC

DQ3

DQ2

DQ1

DQ0

NC

A0

A1

A2

A3

A4

A5

A6

A7

VCAP

WE

A8

A10

A11

A12

A13

A14

A15

A16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

54-pin TSOP II

Top View

(not to scale)

OE

CE

VCC

NC

VSS

NC

A9

NC

54

53

52

51

49

50

HSB

BHE

BLE

DQ15

DQ14

DQ13

DQ12

VSS

DQ11

DQ10

DQ9

DQ8

(

× 16)

[8]

[7]

Pin Definitions

Pin Name

I/O Type

Description

A0–A18

Input

Address inputs. Used to select one of the 524,288 bytes of the nvSRAM for × 8 Configuration.

A0–A17

Address inputs. Used to Select one of the 262,144 words of the nvSRAM for × 16 Configuration.

DQ0–DQ7 Input/Output Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation.

DQ0–DQ15

Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on

operation.

WE

Input

Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific

address location.

CE

Input

Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

OE

Input

Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

cycles. I/O pins are tristated on deasserting OE HIGH.

BHE

Input

Byte High Enable, Active LOW. Controls DQ15–DQ8.

BLE

Input

Byte Low Enable, Active LOW. Controls DQ7–DQ0.

VSS

Ground

Ground for the device. Must be connected to the ground of the system.

VCC

Power supply Power supply inputs to the device.

HSB[9]

Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.

When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware

and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high

current, and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection

optional).

VCAP

Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to

non-volatile elements.

NC

No connect No Connect. This pin is not connected to the die.

Notes

7. Address expansion for 16-Mbit. NC pin not connected to die.

8. Address expansion for 8-Mbit. NC pin not connected to die.

9. HSB pin is not available in 44-pin TSOP II (× 16) package.

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CY14B104NA-BA45XI Datasheet(PDF) 4 Page - Cypress Semiconductor

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