0.1

1.0

10.0

100.0

1000.0

SWITCHING FREQUENCY (kHz)

0.001

0.010

0.100

1.000

LM5102

SNVS268A – MAY 2004 – REVISED MARCH 2013

www.ti.com

LAYOUT CONSIDERATIONS

The optimum performance of high and low side gate drivers cannot be achieved without taking due

considerations during circuit board layout. Following points are emphasized.

2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be

3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the

source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.

4. Grounding considerations:

–

The first priority in designing grounding connections is to confine the high peak currents from charging

and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and

minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as

possible to the gate driver.

–

The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground

referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on

The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length

and area on the circuit board is important to ensure reliable operation.

5. The resistors on the RT1 and RT2 timer pins must be placed very close to the IC and seperated from high

current paths to avoid noise coupling to the time delay generator which could disrupt timer operation.

POWER DISSIPATION CONSIDERATIONS

The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate

2

(1)

There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and

HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load

capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the

power losses driving the output loads and agrees well with the above equation. This plot can be used to

approximate the power losses due to the gate drivers.

Figure 19. Gate Driver Power Dissipation (LO + HO)

10

Submit Documentation Feedback

Copyright © 2004–2013, Texas Instruments Incorporated

Product Folder Links: LM5102