UCC29002

UCC29002/1

UCC39002

SLUS495H − SEPTEMBER 2001 − REVISED AUGUST 2007

10

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FUNCTIONAL DESCRIPTION

start up and adjust logic

The start up and adjust logic responds to unusual operating conditions during start up, fault and disable. Under

these circumstances the information obtainable by the error amplifier of the UCC39002 is not sufficient to make

the right output voltage adjustment, therefore the adjust amplifier is forced to certain known states. Similarly,

the driver amplifier of UCC39002 is disabled during these conditions.

In the UCC39002/UCC29002, during start up, the load share driver amplifier is disabled by the disconnect

switch and the adjust amplifier is forced to sink the maximum current through the adjust resistor. This operating

mode ensures that the module controlled by the UCC39002 will be able to quickly engage in sharing the load

current since its output will be adjusted to a sufficiently high voltage immediately at turn on. Both the load share

driver and the adjust amplifiers revert to normal operation as soon as the measured current exceeds 80% of

the average per module current level represented by the LS bus voltage. The UCC29002/1 does not have this

logic at start up. In this way, the UCC29002/1 will not adjust the output of the module to its maximum adjustment

range at turn on and engages load sharing at more moderate rate.

In case of a fault shorting the load share bus to ground or to the bias of the UCC39002 the load share bus driver

and the adjust amplifiers are disabled. The same action takes place when the UCC39002 is disabled using the

CS+ and CS− pins or when the bias voltage is below the minimum operating voltage.

bias and bias OK circuit (VDD)

The UCC39002 is built on a 15-V, high performance BiCMOS process. Accordingly the maximum voltage across

voltage is 13.5 V which corresponds to the tolerance of the on-board 14.2-V Zener clamp circuit. In case the

bias voltage could exceed the 13.5-V limit, the UCC39002 should be powered through a current limiting resistor.

The bypass capacitor for VDD is also the compensation for the input active clamp of the device and, as such,

must be placed as close to the device pins (VDD and GND) as possible, using a good quality low ESL capacitor,

including trace length. The device is optimized for a capacitor value of 0.1

µF to 1 µF.

UDG−02089

4

GND

3

VDD

+

Bias_OK

VBIAS

(Internal Bias)

14.2 V

4.375 V