UCC2817, UCC2818, UCC3817, UCC3818

BiCMOS POWER FACTOR PREREGULATOR

SLUS395J - FEBRUARY 2000 - REVISED MARCH 2009

10

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APPLICATION INFORMATION

multiplier (continued)

of its linear range. A smaller current level is functional, but noise can become an issue, especially at low input

voltage rating constraints of standard 1/4-W resistor, use a combination of lower value resistors connected in

series to give the required resistance and distribute the high voltage amongst the resistors. For this design

example two 383-k

Ω resistors were used in series.

The current into the IAC pin is mirrored internally to the VFF pin where it is filtered to produce a voltage feed

forward signal proportional to line voltage. The VFF voltage is used to keep the power stage gain constant; and

to provid input power limiting. Please refer to Texas Instruments application note SLUA196 for detailed

explanation on how the VFF pin provides power limiting. The following equation can be used to size the VFF

resistance connected between the IAC pin and the rectified line voltage.

R

VFF +

1.4 V

V

IN(min)

0.9

2

R

IAC

[ 30 kW

Because the VFF voltage is generated from line voltage it needs to be adequately filtered to reduce total

harmonic distortion caused by the 120 Hz rectified line voltage. Refer to Unitrode Power Supply Design

Seminar, SEM−700 Topic 7, [Optimizing the Design of a High Power Factor Preregulator.] A single pole filter

was adequate for this design. Assuming that an allocation of 1.5% total harmonic distortion from this input is

allowed, and that the second harmonic ripple is 66% of the input ac line voltage, the amount of attenuation

required by this filter is:

1.5 %

66 %

+ 0.022

at:

f

P +

120 Hz

0.022

[ 2.6 Hz

filter.

C

VFF +

1

2

p

R

VFF

f

P

[ 2.2 mF

I

MOUT(max) +

I

IAC

@V

IN(min)

V

VAOUT(max) *

1V

K

V

VFF

2

(min)