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BQ27441DRZT-G1B Datasheet(PDF) 8 Page - Texas Instruments |
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BQ27441DRZT-G1B Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 22 page  tSU(STA) SCL SDA tw(H) tw(L) tf tr t(BUF) tr td(STA) REPEATED START th(DAT) tsu(DAT) tf tsu(STOP) STOP START bq27441-G1 SLUSBH1A – NOVEMBER 2013 – REVISED JANUARY 2014 www.ti.com I 2C-COMPATIBLE INTERFACE COMMUNICATION TIMING CHARACTERISTICS TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Standard Mode (100 kHz) td(STA) Start to first falling edge of SCL 4 μs tw(L) SCL pulse duration (low) 4.7 μs tw(H) SCL pulse duration (high) 4 μs tsu(STA) Setup for repeated start 4.7 μs tsu(DAT) Data setup time Host drives SDA 250 ns th(DAT) Data hold time Host drives SDA 0 ns tsu(STOP) Setup time for stop 4 μs t(BUF) Bus free time between stop and Includes Command Waiting Time 66 μs start tf SCL/SDA fall time (1) 300 ns tr SCL/SDA rise time (1) 300 ns fSCL Clock frequency(2) 100 kHz Fast Mode (400 kHz) td(STA) Start to first falling edge of SCL 600 ns tw(L) SCL pulse duration (low) 1300 ns tw(H) SCL pulse duration (high) 600 ns tsu(STA) Setup for repeated start 600 ns tsu(DAT) Data setup time Host drives SDA 100 ns th(DAT) Data hold time Host drives SDA 0 ns tsu(STOP) Setup time for stop 600 ns t(BUF) Bus free time between stop and Includes Command Waiting Time 66 μs start tf SCL/SDA fall time (1) 300 ns tr SCL/SDA rise time (1) 300 ns fSCL Clock frequency(2) 400 kHz (1) Specified by design. Not production tested. (2) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (Refer to I2C INTERFACE and I2C Command Waiting Time) Figure 2. I2C-Compatible Interface Timing Diagrams 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: bq27441-G1 |
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