5-189

FAST AND LS TTL DATA

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These

monolithic dual flip-flops are designed so that when the clock goes HIGH, the

inputs are enabled and data will be accepted. The logic level of the J and K

inputs may be allowed to change when the clock pulse is HIGH and the

bistable will perform according to the truth table as long as minimum setup

times are observed. Input data is transferred to the outputs on the

negative-going edge of the clock pulse.

LOGIC DIAGRAM (Each Flip-Flop)

Q

5(9)

J

3(11)

Q

6(8)

SET (SD)

4(10)

K

2(12)

1(13)

CLOCK (CP)

MODE SELECT — TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

OPERATING MODE

SD

J

K

Q

Q

Set

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

L

H

H

H

H

X

h

l

h

l

X

h

h

l

l

H

q

L

H

q

L

q

H

L

q

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output)

SN54/74LS113A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC SYMBOL

VCC = PIN 14

GND = PIN 7

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

14

1

14

1

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

14

1

D SUFFIX

SOIC

CASE 751A-02

4

3

1

2

5

6

SD

J

CP

K

Q

Q

10

11

9

13

12

8

SD

J

CP

K

Q

Q