Revision 2.4

April 2002

9

BSI

BS616LV4025

R0201-BS616LV4025

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.

All signals must be active to initiate a write and any one signal can terminate

a write by going inactive. The data input setup and hold timing should be referenced to the

second transition edge of the signal that terminates the write.

4. During this period, DQ pins are in the output state so that the input signals of opposite

phase to the outputs must not be applied.

5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions

or after the WE transition, output remain in a high impedance state.

9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the

data input signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured

500mV from steady state with CL = 30pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

±

(11)

(2)

(4,10)

(3)

D

IN

D

OUT

WE

CE1

ADDRESS

(7)

(8)

(8,9)

CE2

LB,UB

(5)

(5)