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AT25010B Datasheet(PDF) 1 Page - ATMEL Corporation

Part # AT25010B
Description  Serial Peripheral Interface (SPI) Compatible
Download  27 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT25010B Datasheet(HTML) 1 Page - ATMEL Corporation

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Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
–V
CC = 1.8V to 5.5V
20 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Green (Pb/Halogen-free/Rohs Compliant) Packaging Options
Die Sales: Wafer Form, Waffle Pack, Bumped Wafers
Description
The AT25010B/020B/040B provides 1024/2048/4096 bits of serial electrically eras-
able programmable read-only memory (EEPROM) organized as 128/256/512 words
of 8 bits each. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The
AT25010B/020B/040B is available in space saving, JEDEC SOIC, UDFN, TSSOP,
XDFN and VFBGA packages.
The AT25010B/020B/040B is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate Program Enable and Program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 0-1.
Pin Configuration
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
V
CC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
SPI Serial
EEPROM
1K (128x8)
2K (256x8)
4K (512x8)
AT25010B
AT25020B
AT25040B
VCC
HOLD
SCK
SI
CS
SO
WP
GND
4
3
2
1
5
6
7
8
8-lead UDFN, XDFN
Bottom View
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
8-ball VFBGA
Bottom View
1
2
3
4
8
7
6
5
SOIC, TSSOP
VCC
HOLD
SCK
SI
CS
SO
WP
GND
8707B–SEEPR–3/10


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