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9

ADS7844

THEORY OF OPERATION

The ADS7844 is a classic successive approximation register

(SAR) analog-to-digital (A/D) converter. The architecture is

based on capacitive redistribution which inherently includes

a sample/hold function. The converter is fabricated on a

0.6

µs CMOS process.

The basic operation of the ADS7844 is shown in Figure 1.

The device requires an external reference and an external

clock. It operates from a single supply of 2.7V to 5.25V. The

external reference can be any voltage between 100mV and

input range of the converter. The average reference input

current depends on the conversion rate of the ADS7844.

The analog input to the converter is differential and is

provided via an eight-channel multiplexer. The input can be

provided in reference to a voltage on the COM pin (which

is generally ground) or differentially by using four of the

eight input channels (CH0 - CH7). The particular configura-

tion is selectable via the digital interface.

A2

A1

A0

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

0

0

0

+IN

–IN

00

1

+IN

–IN

0

1

0

+IN

–IN

01

1

+IN

–IN

10

0

–IN

+IN

1

0

1

–IN

+IN

1

1

0

–IN

+IN

1

1

1

–IN

+IN

TABLE II. Differential Channel Control (SGL/DIF LOW).

TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).

FIGURE 1. Basic Operation of the ADS7844.

A2

A1

A0

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

0

0

0

+IN

–IN

1

0

0

+IN

–IN

00

1

+IN

–IN

1

0

1

+IN

–IN

0

1

0

+IN

–IN

1

1

0

+IN

–IN

0

1

1

+IN

–IN

1

1

1

+IN

–IN

ANALOG INPUT

Figure 2 shows a block diagram of the input multiplexer on

the ADS7844. The differential input of the converter is

derived from one of the eight inputs in reference to the COM

pin or four of the eight inputs. Table I and Table II show the

relationship between the A2, A1, A0, and SGL/DIF control

bits and the configuration of the analog multiplexer. The

control bits are provided serially via the DIN pin, see the

Digital Interface section of this data sheet for more details.

When the converter enters the hold mode, the voltage

difference between the +IN and –IN inputs (see Figure 2) is

captured on the internal capacitor array. The voltage on the

–IN input is limited between –0.2V and 1.25V, allowing the

input to reject small signals which are common to both the

+IN and –IN input. The +IN input has a range of –0.2V to

The input current on the analog inputs depends on the

conversion rate of the device. During the sample period, the

source must charge the internal sampling capacitor (typi-

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SHDN

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

+V

CC

D

CLK

CS

D

IN

BUSY

D

OUT

GND

GND

+V

CC

V

REF

Serial/Conversion Clock

Chip Select

Serial Data In

Serial Data Out

+2.7V to +5V

1

µF to 10µF

ADS7844

Single-ended

or differential

analog inputs

1

µF to 10µF

0.1

µF