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ADS805U Datasheet(PDF) 2 Page - Burr-Brown (TI) |
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ADS805U Datasheet(HTML) 2 Page - Burr-Brown (TI) |
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2 / 12 page  2 ® ADS805 SPECIFICATIONS At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, single-ended input and sampling rate = 20MHz, unless otherwise specified. ADS805U ADS805E PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 12 Bits Guaranteed T(1) Bits SPECIFIED TEMPERATURE RANGE –40 to +85 –40 to +85 °C CONVERSION CHARACTERISTICS Sample Rate 10k 20M TT Samples/s Data Latency 6 T Clk Cycles ANALOG INPUT Standard Single-Ended Input Range 1.5 3.5 TT V Optional Single-Ended Input Range 0 5 TT V Standard Common-Mode Voltage 2.5 T V Standard Optional Common-Mode Voltage 1 T V Input Capacitance 20 T pF Track-Mode Input Bandwidth –3dBFS Input 270 T MHz DYNAMIC CHARACTERISTICS Differential Linearity Error (Largest Code Error) f = 500kHz ±0.25 ±0.75 TT LSB No Missing Codes Guaranteed Guaranteed Spurious Free Dynamic Range(2) f = 9.8MHz 65 74 TT dBFS Two-Tone Intermodulation Distortion(4) f = 7.7MHz and 7.9MHz (–7dB each tone) –70 T dBc Signal-to-Noise Ratio (SNR) f = 9.8MHz 63 68 TT dBFS Signal-to-(Noise + Distortion) (SINAD) f = 9.8MHz 62 66 TT dBFS Effective Number of Bits at 9.8MHz(5) 10.7 T Bits Input Referred Noise 0V to 5V Input 0.09 T LSBs rms 1.5V to 3.5V Input 0.23 T LSBs rms Integral Nonlinearity Error f = 500kHz ±1 ±2 TT LSB Aperture Delay Time 3 T ns Aperture Jitter 4 T ps rms Overvoltage Recovery Time 1.5X FS Input 2 T ns Full-Scale Step Acquisition Time 20 20 ns DIGITAL INPUTS Logic Family Convert Command Start Conversion High Level Input Current (VIN = 5V)(6) ±100 T µA Low Level Input Current (VIN = 0V) 10 T µA High Level Input Voltage +3.5 T V Low Level Input Voltage +1.0 T V Input Capacitance 5 T pF DIGITAL OUTPUTS Logic Family Logic Coding Low Output Voltage (IOL = 50µA) 0.1 T V Low Output Voltage (IOL = 1.6mA) 0.4 T V High Output Voltage (IOH = 50µA) +4.5 T V High Output Voltage (IOH = 0.5mA) +2.4 T V 3-State Enable Time OE = L 20 40 TT ns 3-State Disable Time OE = H 2 10 TT ns Output Capacitance 5 T pF ACCURACY (5Vp-p Input Range) Zero Error (Referred to –FS) At 25 °C 0.3 ±1.5 TT %FS Zero Error Drift (Referred to –FS) ±5 T ppm/ °C Gain Error(7) At 25 °C 0.7 ±2.0 T %FS Gain Error Drift(7) ±18 T ppm/ °C Gain Error(8) At 25 °C 0.2 ±1.5 T %FS Gain Error Drift(8) ±10 T ppm/ °C Power Supply Rejection of Gain ∆ V S = ±5% 60 70 TT dB Reference Input Resistance 1.6 T k Ω Internal Voltage Reference Tolerance (VREF = 2.5V) At 25 °C ±35 T mV Internal Voltage Reference Tolerance (VREF = 1.0V) At 25 °C ±14 T mV CMOS/TTL Compatible Straight Offset Binary CMOS/TTL Compatible Straight Offset Binary CMOS Compatible Rising Edge of Convert Clock CMOS Compatible Rising Edge of Convert Clock |
Similar Part No. - ADS805U |
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Similar Description - ADS805U |
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